Chen-Yu Tsai cfe4c93b58 clk: sunxi: add correct divider table for sun4i-apb0 clock ... The sun4i-apb0 clock, as found on all platforms using it, is a power-of-two-based divider clock, with a special divider of 2 for value 0. This was causing the clock framework to incorrectly calculate the clock rate for apb1 and related modules on sun6i and sun8i. On sun[4/5/7]i, u-boot SPL configures the divider with value 1 for /2 divider, so no suprises there. This patch adds a proper divider table for it, so the correct clock rate can be calculated. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>		2014-09-13 10:07:24 +02:00
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clk-a10-hosc.c	clk: sunxi: Move the 24M oscillator to a file of its own	2014-06-11 09:58:44 +02:00
clk-a20-gmac.c	clk: sunxi: add __iomem markings to MMIO pointers	2014-07-28 15:39:05 -07:00
clk-factors.c	clk: sunxi: Support factor clocks with N factor starting not from 0	2014-07-04 12:05:12 +02:00
clk-factors.h	clk: sunxi: Support factor clocks with N factor starting not from 0	2014-07-04 12:05:12 +02:00
clk-sun6i-apb0-gates.c	clk: sunxi: staticize structures and arrays	2014-07-28 15:39:22 -07:00
clk-sun6i-apb0.c	clk: sunxi: staticize structures and arrays	2014-07-28 15:39:22 -07:00
clk-sun6i-ar100.c	clk: sunxi: staticize structures and arrays	2014-07-28 15:39:22 -07:00
clk-sun8i-apb0.c	clk: sunxi: staticize structures and arrays	2014-07-28 15:39:22 -07:00
clk-sunxi.c	clk: sunxi: add correct divider table for sun4i-apb0 clock	2014-09-13 10:07:24 +02:00
Makefile	clk: sunxi: Add A23 APB0 divider clock support	2014-07-07 10:46:21 +02:00