mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 20:36:49 +07:00
74f330bcea
Since commit 30832ab56 ("mmc: sdhci: Always pass clock request value
zero to set_clock host op") was merged, esdhc_set_clock starts hitting
"if (clock == 0)" where ESDHC_SYSTEM_CONTROL has been operated. This
causes SDHCI card-detection function being broken. Fix the regression
by moving "if (clock == 0)" above ESDHC_SYSTEM_CONTROL operation.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: <stable@vger.kernel.org>
Signed-off-by: Chris Ball <cjb@laptop.org>
82 lines
2.2 KiB
C
82 lines
2.2 KiB
C
/*
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* Freescale eSDHC controller driver generics for OF and pltfm.
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*
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* Copyright (c) 2007 Freescale Semiconductor, Inc.
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* Copyright (c) 2009 MontaVista Software, Inc.
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* Copyright (c) 2010 Pengutronix e.K.
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* Author: Wolfram Sang <w.sang@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*/
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#ifndef _DRIVERS_MMC_SDHCI_ESDHC_H
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#define _DRIVERS_MMC_SDHCI_ESDHC_H
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/*
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* Ops and quirks for the Freescale eSDHC controller.
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*/
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#define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
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SDHCI_QUIRK_NO_BUSY_IRQ | \
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SDHCI_QUIRK_NONSTANDARD_CLOCK | \
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SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
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SDHCI_QUIRK_PIO_NEEDS_DELAY | \
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SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
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#define ESDHC_SYSTEM_CONTROL 0x2c
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#define ESDHC_CLOCK_MASK 0x0000fff0
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#define ESDHC_PREDIV_SHIFT 8
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#define ESDHC_DIVIDER_SHIFT 4
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#define ESDHC_CLOCK_PEREN 0x00000004
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#define ESDHC_CLOCK_HCKEN 0x00000002
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#define ESDHC_CLOCK_IPGEN 0x00000001
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/* pltfm-specific */
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#define ESDHC_HOST_CONTROL_LE 0x20
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/* OF-specific */
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#define ESDHC_DMA_SYSCTL 0x40c
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#define ESDHC_DMA_SNOOP 0x00000040
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#define ESDHC_HOST_CONTROL_RES 0x05
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static inline void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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int pre_div = 2;
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int div = 1;
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u32 temp;
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if (clock == 0)
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goto out;
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temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
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temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
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| ESDHC_CLOCK_MASK);
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sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
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while (host->max_clk / pre_div / 16 > clock && pre_div < 256)
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pre_div *= 2;
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while (host->max_clk / pre_div / div > clock && div < 16)
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div++;
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dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
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clock, host->max_clk / pre_div / div);
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pre_div >>= 1;
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div--;
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temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
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temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
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| (div << ESDHC_DIVIDER_SHIFT)
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| (pre_div << ESDHC_PREDIV_SHIFT));
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sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
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mdelay(1);
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out:
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host->clock = clock;
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}
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#endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */
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