mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 17:22:01 +07:00
cfafe26013
Currently, all harts have to jump Linux in RISC-V. This complicates the multi-stage boot process as every transient stage also has to ensure all harts enter to that stage and jump to Linux afterwards. It also obstructs a clean Kexec implementation. SBI HSM extension provides alternate solutions where only a single hart need to boot and enter Linux. The booting hart can bring up secondary harts one by one afterwards. Add SBI HSM based cpu_ops that implements an ordered booting method in RISC-V. This change is also backward compatible with older firmware not implementing HSM extension. If a latest kernel is used with older firmware, it will continue to use the default spinning booting method. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
54 lines
1.2 KiB
Makefile
54 lines
1.2 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0-only
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#
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# Makefile for the RISC-V Linux kernel
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#
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ifdef CONFIG_FTRACE
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CFLAGS_REMOVE_ftrace.o = -pg
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CFLAGS_REMOVE_patch.o = -pg
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endif
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extra-y += head.o
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extra-y += vmlinux.lds
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obj-y += cpu.o
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obj-y += cpufeature.o
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obj-y += entry.o
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obj-y += irq.o
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obj-y += process.o
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obj-y += ptrace.o
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obj-y += reset.o
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obj-y += setup.o
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obj-y += signal.o
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obj-y += syscall_table.o
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obj-y += sys_riscv.o
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obj-y += time.o
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obj-y += traps.o
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obj-y += riscv_ksyms.o
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obj-y += stacktrace.o
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obj-y += cacheinfo.o
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obj-y += patch.o
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obj-$(CONFIG_MMU) += vdso.o vdso/
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obj-$(CONFIG_RISCV_M_MODE) += clint.o
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obj-$(CONFIG_FPU) += fpu.o
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obj-$(CONFIG_SMP) += smpboot.o
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obj-$(CONFIG_SMP) += smp.o
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obj-$(CONFIG_SMP) += cpu_ops.o
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obj-$(CONFIG_SMP) += cpu_ops_spinwait.o
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obj-$(CONFIG_MODULES) += module.o
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obj-$(CONFIG_MODULE_SECTIONS) += module-sections.o
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obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
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obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o
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obj-$(CONFIG_PERF_EVENTS) += perf_event.o
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obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o
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obj-$(CONFIG_HAVE_PERF_REGS) += perf_regs.o
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obj-$(CONFIG_RISCV_SBI) += sbi.o
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ifeq ($(CONFIG_RISCV_SBI), y)
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obj-$(CONFIG_SMP) += cpu_ops_sbi.o
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endif
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clean:
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