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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
ac8fd122e0
request_irq() is preferred over setup_irq(). Invocations of setup_irq() occur after memory allocators are ready. Per tglx[1], setup_irq() existed in olden days when allocators were not ready by the time early interrupts were initialized. Hence replace setup_irq() by request_irq(). remove_irq() has been replaced by free_irq() as well. There were build error's during previous version, couple of which was reported by kbuild test robot <lkp@intel.com> of which one was reported by Thomas Bogendoerfer <tsbogend@alpha.franken.de> as well. There were a few more issues including build errors, those also have been fixed. [1] https://lkml.kernel.org/r/alpine.DEB.2.20.1710191609480.1971@nanos Signed-off-by: afzal mohammed <afzal.mohd.ma@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
224 lines
6.4 KiB
C
224 lines
6.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
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* Copyright (C) 2001 Ralf Baechle
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* Copyright (C) 2013 Imagination Technologies Ltd.
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*
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* Routines for generic manipulation of the interrupts found on the MIPS
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* Malta board. The interrupt controller is located in the South Bridge
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* a PIIX4 device with two internal 82C95 interrupt controllers.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of_irq.h>
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#include <linux/kernel_stat.h>
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#include <linux/kernel.h>
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#include <linux/random.h>
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#include <asm/traps.h>
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#include <asm/i8259.h>
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#include <asm/irq_cpu.h>
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#include <asm/irq_regs.h>
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#include <asm/mips-boards/malta.h>
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#include <asm/mips-boards/maltaint.h>
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#include <asm/mips-cps.h>
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#include <asm/gt64120.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/msc01_pci.h>
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#include <asm/msc01_ic.h>
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#include <asm/setup.h>
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#include <asm/rtlx.h>
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static inline int mips_pcibios_iack(void)
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{
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int irq;
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/*
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* Determine highest priority pending interrupt by performing
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* a PCI Interrupt Acknowledge cycle.
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*/
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switch (mips_revision_sconid) {
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case MIPS_REVISION_SCON_SOCIT:
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case MIPS_REVISION_SCON_ROCIT:
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case MIPS_REVISION_SCON_SOCITSC:
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case MIPS_REVISION_SCON_SOCITSCP:
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MSC_READ(MSC01_PCI_IACK, irq);
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irq &= 0xff;
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break;
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case MIPS_REVISION_SCON_GT64120:
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irq = GT_READ(GT_PCI0_IACK_OFS);
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irq &= 0xff;
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break;
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case MIPS_REVISION_SCON_BONITO:
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/* The following will generate a PCI IACK cycle on the
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* Bonito controller. It's a little bit kludgy, but it
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* was the easiest way to implement it in hardware at
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* the given time.
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*/
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BONITO_PCIMAP_CFG = 0x20000;
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/* Flush Bonito register block */
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(void) BONITO_PCIMAP_CFG;
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iob(); /* sync */
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irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
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iob(); /* sync */
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irq &= 0xff;
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BONITO_PCIMAP_CFG = 0;
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break;
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default:
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pr_emerg("Unknown system controller.\n");
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return -1;
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}
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return irq;
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}
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static void corehi_irqdispatch(void)
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{
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unsigned int intedge, intsteer, pcicmd, pcibadaddr;
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unsigned int pcimstat, intisr, inten, intpol;
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unsigned int intrcause, datalo, datahi;
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struct pt_regs *regs = get_irq_regs();
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pr_emerg("CoreHI interrupt, shouldn't happen, we die here!\n");
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pr_emerg("epc : %08lx\nStatus: %08lx\n"
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"Cause : %08lx\nbadVaddr : %08lx\n",
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regs->cp0_epc, regs->cp0_status,
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regs->cp0_cause, regs->cp0_badvaddr);
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/* Read all the registers and then print them as there is a
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problem with interspersed printk's upsetting the Bonito controller.
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Do it for the others too.
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*/
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switch (mips_revision_sconid) {
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case MIPS_REVISION_SCON_SOCIT:
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case MIPS_REVISION_SCON_ROCIT:
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case MIPS_REVISION_SCON_SOCITSC:
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case MIPS_REVISION_SCON_SOCITSCP:
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ll_msc_irq();
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break;
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case MIPS_REVISION_SCON_GT64120:
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intrcause = GT_READ(GT_INTRCAUSE_OFS);
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datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
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datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
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pr_emerg("GT_INTRCAUSE = %08x\n", intrcause);
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pr_emerg("GT_CPUERR_ADDR = %02x%08x\n",
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datahi, datalo);
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break;
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case MIPS_REVISION_SCON_BONITO:
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pcibadaddr = BONITO_PCIBADADDR;
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pcimstat = BONITO_PCIMSTAT;
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intisr = BONITO_INTISR;
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inten = BONITO_INTEN;
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intpol = BONITO_INTPOL;
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intedge = BONITO_INTEDGE;
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intsteer = BONITO_INTSTEER;
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pcicmd = BONITO_PCICMD;
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pr_emerg("BONITO_INTISR = %08x\n", intisr);
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pr_emerg("BONITO_INTEN = %08x\n", inten);
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pr_emerg("BONITO_INTPOL = %08x\n", intpol);
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pr_emerg("BONITO_INTEDGE = %08x\n", intedge);
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pr_emerg("BONITO_INTSTEER = %08x\n", intsteer);
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pr_emerg("BONITO_PCICMD = %08x\n", pcicmd);
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pr_emerg("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
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pr_emerg("BONITO_PCIMSTAT = %08x\n", pcimstat);
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break;
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}
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die("CoreHi interrupt", regs);
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}
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static irqreturn_t corehi_handler(int irq, void *dev_id)
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{
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corehi_irqdispatch();
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return IRQ_HANDLED;
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}
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static msc_irqmap_t msc_irqmap[] __initdata = {
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{MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
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{MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
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};
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static int msc_nr_irqs __initdata = ARRAY_SIZE(msc_irqmap);
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static msc_irqmap_t msc_eicirqmap[] __initdata = {
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{MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
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{MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
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};
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static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap);
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void __init arch_init_irq(void)
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{
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int corehi_irq;
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/*
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* Preallocate the i8259's expected virq's here. Since irqchip_init()
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* will probe the irqchips in hierarchial order, i8259 is probed last.
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* If anything allocates a virq before the i8259 is probed, it will
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* be given one of the i8259's expected range and consequently setup
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* of the i8259 will fail.
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*/
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WARN(irq_alloc_descs(I8259A_IRQ_BASE, I8259A_IRQ_BASE,
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16, numa_node_id()) < 0,
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"Cannot reserve i8259 virqs at IRQ%d\n", I8259A_IRQ_BASE);
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i8259_set_poll(mips_pcibios_iack);
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irqchip_init();
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switch (mips_revision_sconid) {
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case MIPS_REVISION_SCON_SOCIT:
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case MIPS_REVISION_SCON_ROCIT:
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if (cpu_has_veic)
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init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
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MSC01E_INT_BASE, msc_eicirqmap,
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msc_nr_eicirqs);
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else
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init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
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MSC01C_INT_BASE, msc_irqmap,
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msc_nr_irqs);
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break;
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case MIPS_REVISION_SCON_SOCITSC:
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case MIPS_REVISION_SCON_SOCITSCP:
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if (cpu_has_veic)
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init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
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MSC01E_INT_BASE, msc_eicirqmap,
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msc_nr_eicirqs);
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else
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init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
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MSC01C_INT_BASE, msc_irqmap,
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msc_nr_irqs);
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}
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if (mips_gic_present()) {
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corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
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} else if (cpu_has_veic) {
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set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
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corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI;
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} else {
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corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
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}
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if (request_irq(corehi_irq, corehi_handler, IRQF_NO_THREAD, "CoreHi",
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NULL))
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pr_err("Failed to request irq %d (CoreHi)\n", corehi_irq);
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}
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