mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 23:45:19 +07:00
e1eb899b45
Add the IOCTL interface so that applications can allocate per VM BOs. Still WIP since not all corner cases are tested yet, but this reduces average CS overhead for 10K BOs from 21ms down to 48us. v2: add some extra checks, remove the WIP tag v3: rename new flag to AMDGPU_GEM_CREATE_VM_ALWAYS_VALID Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
145 lines
3.9 KiB
C
145 lines
3.9 KiB
C
/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* based on nouveau_prime.c
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*
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* Authors: Alex Deucher
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*/
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include <drm/amdgpu_drm.h>
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#include <linux/dma-buf.h>
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struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj)
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{
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struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
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int npages = bo->tbo.num_pages;
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return drm_prime_pages_to_sg(bo->tbo.ttm->pages, npages);
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}
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void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj)
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{
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struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
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int ret;
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ret = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages,
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&bo->dma_buf_vmap);
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if (ret)
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return ERR_PTR(ret);
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return bo->dma_buf_vmap.virtual;
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}
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void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
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{
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struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
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ttm_bo_kunmap(&bo->dma_buf_vmap);
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}
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struct drm_gem_object *
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amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
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struct dma_buf_attachment *attach,
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struct sg_table *sg)
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{
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struct reservation_object *resv = attach->dmabuf->resv;
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struct amdgpu_device *adev = dev->dev_private;
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struct amdgpu_bo *bo;
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int ret;
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ww_mutex_lock(&resv->lock, NULL);
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ret = amdgpu_bo_create(adev, attach->dmabuf->size, PAGE_SIZE, false,
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AMDGPU_GEM_DOMAIN_GTT, 0, sg, resv, 0, &bo);
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ww_mutex_unlock(&resv->lock);
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if (ret)
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return ERR_PTR(ret);
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bo->prime_shared_count = 1;
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return &bo->gem_base;
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}
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int amdgpu_gem_prime_pin(struct drm_gem_object *obj)
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{
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struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
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long ret = 0;
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ret = amdgpu_bo_reserve(bo, false);
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if (unlikely(ret != 0))
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return ret;
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/*
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* Wait for all shared fences to complete before we switch to future
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* use of exclusive fence on this prime shared bo.
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*/
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ret = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, false,
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MAX_SCHEDULE_TIMEOUT);
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if (unlikely(ret < 0)) {
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DRM_DEBUG_PRIME("Fence wait failed: %li\n", ret);
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amdgpu_bo_unreserve(bo);
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return ret;
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}
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/* pin buffer into GTT */
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ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, NULL);
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if (likely(ret == 0))
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bo->prime_shared_count++;
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amdgpu_bo_unreserve(bo);
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return ret;
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}
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void amdgpu_gem_prime_unpin(struct drm_gem_object *obj)
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{
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struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
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int ret = 0;
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ret = amdgpu_bo_reserve(bo, true);
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if (unlikely(ret != 0))
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return;
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amdgpu_bo_unpin(bo);
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if (bo->prime_shared_count)
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bo->prime_shared_count--;
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amdgpu_bo_unreserve(bo);
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}
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struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *obj)
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{
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struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
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return bo->tbo.resv;
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}
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struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
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struct drm_gem_object *gobj,
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int flags)
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{
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struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
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if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
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bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
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return ERR_PTR(-EPERM);
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return drm_gem_prime_export(dev, gobj, flags);
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}
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