mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 08:46:45 +07:00
4bdc0d676a
ioremap has provided non-cached semantics by default since the Linux 2.6 days, so remove the additional ioremap_nocache interface. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Arnd Bergmann <arnd@arndb.de>
155 lines
3.2 KiB
C
155 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* mmconfig.c - Low-level direct PCI config space access via MMCONFIG
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*
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* This is an 64bit optimized version that always keeps the full mmconfig
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* space mapped. This allows lockless config space operation.
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*/
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/acpi.h>
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#include <linux/bitmap.h>
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#include <linux/rcupdate.h>
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#include <asm/e820/api.h>
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#include <asm/pci_x86.h>
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#define PREFIX "PCI: "
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static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
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{
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struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus);
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if (cfg && cfg->virt)
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return cfg->virt + (PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12));
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return NULL;
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}
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static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
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unsigned int devfn, int reg, int len, u32 *value)
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{
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char __iomem *addr;
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/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
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if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) {
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err: *value = -1;
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return -EINVAL;
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}
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rcu_read_lock();
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addr = pci_dev_base(seg, bus, devfn);
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if (!addr) {
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rcu_read_unlock();
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goto err;
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}
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switch (len) {
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case 1:
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*value = mmio_config_readb(addr + reg);
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break;
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case 2:
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*value = mmio_config_readw(addr + reg);
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break;
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case 4:
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*value = mmio_config_readl(addr + reg);
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break;
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}
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rcu_read_unlock();
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return 0;
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}
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static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
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unsigned int devfn, int reg, int len, u32 value)
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{
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char __iomem *addr;
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/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
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if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095)))
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return -EINVAL;
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rcu_read_lock();
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addr = pci_dev_base(seg, bus, devfn);
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if (!addr) {
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rcu_read_unlock();
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return -EINVAL;
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}
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switch (len) {
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case 1:
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mmio_config_writeb(addr + reg, value);
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break;
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case 2:
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mmio_config_writew(addr + reg, value);
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break;
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case 4:
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mmio_config_writel(addr + reg, value);
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break;
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}
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rcu_read_unlock();
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return 0;
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}
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const struct pci_raw_ops pci_mmcfg = {
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.read = pci_mmcfg_read,
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.write = pci_mmcfg_write,
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};
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static void __iomem *mcfg_ioremap(struct pci_mmcfg_region *cfg)
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{
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void __iomem *addr;
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u64 start, size;
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int num_buses;
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start = cfg->address + PCI_MMCFG_BUS_OFFSET(cfg->start_bus);
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num_buses = cfg->end_bus - cfg->start_bus + 1;
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size = PCI_MMCFG_BUS_OFFSET(num_buses);
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addr = ioremap(start, size);
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if (addr)
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addr -= PCI_MMCFG_BUS_OFFSET(cfg->start_bus);
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return addr;
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}
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int __init pci_mmcfg_arch_init(void)
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{
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struct pci_mmcfg_region *cfg;
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list_for_each_entry(cfg, &pci_mmcfg_list, list)
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if (pci_mmcfg_arch_map(cfg)) {
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pci_mmcfg_arch_free();
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return 0;
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}
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raw_pci_ext_ops = &pci_mmcfg;
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return 1;
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}
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void __init pci_mmcfg_arch_free(void)
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{
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struct pci_mmcfg_region *cfg;
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list_for_each_entry(cfg, &pci_mmcfg_list, list)
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pci_mmcfg_arch_unmap(cfg);
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}
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int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg)
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{
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cfg->virt = mcfg_ioremap(cfg);
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if (!cfg->virt) {
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pr_err(PREFIX "can't map MMCONFIG at %pR\n", &cfg->res);
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return -ENOMEM;
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}
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return 0;
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}
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void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg)
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{
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if (cfg && cfg->virt) {
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iounmap(cfg->virt + PCI_MMCFG_BUS_OFFSET(cfg->start_bus));
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cfg->virt = NULL;
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}
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}
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