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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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8bbe833a65
Some of the PHY and MDIO drivers refer to the COPYING file in the main directory of this archive. This is the main license for Linux, thus GPLv2 plus syscall extension. Fixup the MODULE_LICENSE() where needed and add an SDPX header for GPLv2. Cc: David Daney <david.daney@cavium.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
151 lines
3.4 KiB
C
151 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2009-2016 Cavium, Inc.
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*/
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#include <linux/delay.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/io.h>
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#include "mdio-cavium.h"
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static void cavium_mdiobus_set_mode(struct cavium_mdiobus *p,
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enum cavium_mdiobus_mode m)
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{
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union cvmx_smix_clk smi_clk;
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if (m == p->mode)
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return;
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smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK);
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smi_clk.s.mode = (m == C45) ? 1 : 0;
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smi_clk.s.preamble = 1;
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oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK);
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p->mode = m;
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}
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static int cavium_mdiobus_c45_addr(struct cavium_mdiobus *p,
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int phy_id, int regnum)
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{
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union cvmx_smix_cmd smi_cmd;
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union cvmx_smix_wr_dat smi_wr;
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int timeout = 1000;
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cavium_mdiobus_set_mode(p, C45);
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smi_wr.u64 = 0;
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smi_wr.s.dat = regnum & 0xffff;
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oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);
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regnum = (regnum >> 16) & 0x1f;
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smi_cmd.u64 = 0;
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smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_45_ADDRESS */
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smi_cmd.s.phy_adr = phy_id;
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smi_cmd.s.reg_adr = regnum;
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oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
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do {
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/* Wait 1000 clocks so we don't saturate the RSL bus
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* doing reads.
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*/
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__delay(1000);
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smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
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} while (smi_wr.s.pending && --timeout);
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if (timeout <= 0)
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return -EIO;
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return 0;
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}
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int cavium_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
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{
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struct cavium_mdiobus *p = bus->priv;
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union cvmx_smix_cmd smi_cmd;
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union cvmx_smix_rd_dat smi_rd;
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unsigned int op = 1; /* MDIO_CLAUSE_22_READ */
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int timeout = 1000;
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if (regnum & MII_ADDR_C45) {
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int r = cavium_mdiobus_c45_addr(p, phy_id, regnum);
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if (r < 0)
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return r;
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regnum = (regnum >> 16) & 0x1f;
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op = 3; /* MDIO_CLAUSE_45_READ */
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} else {
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cavium_mdiobus_set_mode(p, C22);
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}
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smi_cmd.u64 = 0;
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smi_cmd.s.phy_op = op;
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smi_cmd.s.phy_adr = phy_id;
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smi_cmd.s.reg_adr = regnum;
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oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
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do {
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/* Wait 1000 clocks so we don't saturate the RSL bus
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* doing reads.
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*/
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__delay(1000);
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smi_rd.u64 = oct_mdio_readq(p->register_base + SMI_RD_DAT);
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} while (smi_rd.s.pending && --timeout);
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if (smi_rd.s.val)
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return smi_rd.s.dat;
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else
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return -EIO;
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}
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EXPORT_SYMBOL(cavium_mdiobus_read);
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int cavium_mdiobus_write(struct mii_bus *bus, int phy_id, int regnum, u16 val)
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{
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struct cavium_mdiobus *p = bus->priv;
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union cvmx_smix_cmd smi_cmd;
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union cvmx_smix_wr_dat smi_wr;
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unsigned int op = 0; /* MDIO_CLAUSE_22_WRITE */
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int timeout = 1000;
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if (regnum & MII_ADDR_C45) {
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int r = cavium_mdiobus_c45_addr(p, phy_id, regnum);
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if (r < 0)
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return r;
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regnum = (regnum >> 16) & 0x1f;
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op = 1; /* MDIO_CLAUSE_45_WRITE */
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} else {
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cavium_mdiobus_set_mode(p, C22);
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}
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smi_wr.u64 = 0;
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smi_wr.s.dat = val;
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oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);
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smi_cmd.u64 = 0;
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smi_cmd.s.phy_op = op;
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smi_cmd.s.phy_adr = phy_id;
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smi_cmd.s.reg_adr = regnum;
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oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);
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do {
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/* Wait 1000 clocks so we don't saturate the RSL bus
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* doing reads.
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*/
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__delay(1000);
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smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT);
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} while (smi_wr.s.pending && --timeout);
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if (timeout <= 0)
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return -EIO;
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return 0;
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}
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EXPORT_SYMBOL(cavium_mdiobus_write);
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MODULE_DESCRIPTION("Common code for OCTEON and Thunder MDIO bus drivers");
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MODULE_AUTHOR("David Daney");
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MODULE_LICENSE("GPL v2");
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