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d4b2cfb8c2
No need to define it globally as we're only using it in wopcm.c Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190807170034.8440-6-michal.wajdeczko@intel.com
232 lines
6.9 KiB
C
232 lines
6.9 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2017-2018 Intel Corporation
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*/
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#include "intel_wopcm.h"
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#include "i915_drv.h"
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/**
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* DOC: WOPCM Layout
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*
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* The layout of the WOPCM will be fixed after writing to GuC WOPCM size and
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* offset registers whose values are calculated and determined by HuC/GuC
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* firmware size and set of hardware requirements/restrictions as shown below:
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*
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* ::
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*
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* +=========> +====================+ <== WOPCM Top
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* ^ | HW contexts RSVD |
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* | +===> +====================+ <== GuC WOPCM Top
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* | ^ | |
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* | | | |
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* | | | |
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* | GuC | |
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* | WOPCM | |
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* | Size +--------------------+
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* WOPCM | | GuC FW RSVD |
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* | | +--------------------+
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* | | | GuC Stack RSVD |
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* | | +------------------- +
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* | v | GuC WOPCM RSVD |
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* | +===> +====================+ <== GuC WOPCM base
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* | | WOPCM RSVD |
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* | +------------------- + <== HuC Firmware Top
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* v | HuC FW |
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* +=========> +====================+ <== WOPCM Base
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*
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* GuC accessible WOPCM starts at GuC WOPCM base and ends at GuC WOPCM top.
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* The top part of the WOPCM is reserved for hardware contexts (e.g. RC6
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* context).
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*/
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/* Default WOPCM size is 2MB from Gen11, 1MB on previous platforms */
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#define GEN11_WOPCM_SIZE SZ_2M
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#define GEN9_WOPCM_SIZE SZ_1M
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/* 16KB WOPCM (RSVD WOPCM) is reserved from HuC firmware top. */
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#define WOPCM_RESERVED_SIZE SZ_16K
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/* 16KB reserved at the beginning of GuC WOPCM. */
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#define GUC_WOPCM_RESERVED SZ_16K
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/* 8KB from GUC_WOPCM_RESERVED is reserved for GuC stack. */
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#define GUC_WOPCM_STACK_RESERVED SZ_8K
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/* GuC WOPCM Offset value needs to be aligned to 16KB. */
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#define GUC_WOPCM_OFFSET_ALIGNMENT (1UL << GUC_WOPCM_OFFSET_SHIFT)
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/* 24KB at the end of WOPCM is reserved for RC6 CTX on BXT. */
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#define BXT_WOPCM_RC6_CTX_RESERVED (SZ_16K + SZ_8K)
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/* 36KB WOPCM reserved at the end of WOPCM on CNL. */
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#define CNL_WOPCM_HW_CTX_RESERVED (SZ_32K + SZ_4K)
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/* 128KB from GUC_WOPCM_RESERVED is reserved for FW on Gen9. */
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#define GEN9_GUC_FW_RESERVED SZ_128K
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#define GEN9_GUC_WOPCM_OFFSET (GUC_WOPCM_RESERVED + GEN9_GUC_FW_RESERVED)
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static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
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{
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return container_of(wopcm, struct drm_i915_private, wopcm);
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}
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/**
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* intel_wopcm_init_early() - Early initialization of the WOPCM.
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* @wopcm: pointer to intel_wopcm.
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*
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* Setup the size of WOPCM which will be used by later on WOPCM partitioning.
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*/
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void intel_wopcm_init_early(struct intel_wopcm *wopcm)
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{
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struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
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if (!HAS_GT_UC(i915))
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return;
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if (INTEL_GEN(i915) >= 11)
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wopcm->size = GEN11_WOPCM_SIZE;
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else
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wopcm->size = GEN9_WOPCM_SIZE;
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DRM_DEBUG_DRIVER("WOPCM size: %uKiB\n", wopcm->size / 1024);
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}
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static inline u32 context_reserved_size(struct drm_i915_private *i915)
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{
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if (IS_GEN9_LP(i915))
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return BXT_WOPCM_RC6_CTX_RESERVED;
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else if (INTEL_GEN(i915) >= 10)
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return CNL_WOPCM_HW_CTX_RESERVED;
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else
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return 0;
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}
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static inline int gen9_check_dword_gap(u32 guc_wopcm_base, u32 guc_wopcm_size)
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{
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u32 offset;
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/*
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* GuC WOPCM size shall be at least a dword larger than the offset from
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* WOPCM base (GuC WOPCM offset from WOPCM base + GEN9_GUC_WOPCM_OFFSET)
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* due to hardware limitation on Gen9.
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*/
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offset = guc_wopcm_base + GEN9_GUC_WOPCM_OFFSET;
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if (offset > guc_wopcm_size ||
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(guc_wopcm_size - offset) < sizeof(u32)) {
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DRM_ERROR("GuC WOPCM size %uKiB is too small. %uKiB needed.\n",
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guc_wopcm_size / 1024,
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(u32)(offset + sizeof(u32)) / 1024);
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return -E2BIG;
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}
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return 0;
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}
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static inline int gen9_check_huc_fw_fits(u32 guc_wopcm_size, u32 huc_fw_size)
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{
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/*
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* On Gen9 & CNL A0, hardware requires the total available GuC WOPCM
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* size to be larger than or equal to HuC firmware size. Otherwise,
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* firmware uploading would fail.
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*/
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if (huc_fw_size > guc_wopcm_size - GUC_WOPCM_RESERVED) {
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DRM_ERROR("HuC FW (%uKiB) won't fit in GuC WOPCM (%uKiB).\n",
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huc_fw_size / 1024,
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(guc_wopcm_size - GUC_WOPCM_RESERVED) / 1024);
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return -E2BIG;
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}
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return 0;
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}
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static inline int check_hw_restriction(struct drm_i915_private *i915,
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u32 guc_wopcm_base, u32 guc_wopcm_size,
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u32 huc_fw_size)
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{
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int err = 0;
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if (IS_GEN(i915, 9))
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err = gen9_check_dword_gap(guc_wopcm_base, guc_wopcm_size);
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if (!err &&
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(IS_GEN(i915, 9) || IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0)))
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err = gen9_check_huc_fw_fits(guc_wopcm_size, huc_fw_size);
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return err;
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}
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/**
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* intel_wopcm_init() - Initialize the WOPCM structure.
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* @wopcm: pointer to intel_wopcm.
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*
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* This function will partition WOPCM space based on GuC and HuC firmware sizes
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* and will allocate max remaining for use by GuC. This function will also
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* enforce platform dependent hardware restrictions on GuC WOPCM offset and
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* size. It will fail the WOPCM init if any of these checks fail, so that the
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* following WOPCM registers setup and GuC firmware uploading would be aborted.
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*/
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void intel_wopcm_init(struct intel_wopcm *wopcm)
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{
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struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
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u32 guc_fw_size = intel_uc_fw_get_upload_size(&i915->gt.uc.guc.fw);
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u32 huc_fw_size = intel_uc_fw_get_upload_size(&i915->gt.uc.huc.fw);
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u32 ctx_rsvd = context_reserved_size(i915);
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u32 guc_wopcm_base;
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u32 guc_wopcm_size;
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u32 guc_wopcm_rsvd;
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int err;
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if (!guc_fw_size)
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return;
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GEM_BUG_ON(!wopcm->size);
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GEM_BUG_ON(wopcm->guc.base);
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GEM_BUG_ON(wopcm->guc.size);
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if (i915_inject_probe_failure(i915))
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return;
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if (guc_fw_size >= wopcm->size) {
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DRM_ERROR("GuC FW (%uKiB) is too big to fit in WOPCM.",
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guc_fw_size / 1024);
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return;
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}
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if (huc_fw_size >= wopcm->size) {
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DRM_ERROR("HuC FW (%uKiB) is too big to fit in WOPCM.",
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huc_fw_size / 1024);
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return;
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}
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guc_wopcm_base = ALIGN(huc_fw_size + WOPCM_RESERVED_SIZE,
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GUC_WOPCM_OFFSET_ALIGNMENT);
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if ((guc_wopcm_base + ctx_rsvd) >= wopcm->size) {
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DRM_ERROR("GuC WOPCM base (%uKiB) is too big.\n",
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guc_wopcm_base / 1024);
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return;
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}
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guc_wopcm_size = wopcm->size - guc_wopcm_base - ctx_rsvd;
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guc_wopcm_size &= GUC_WOPCM_SIZE_MASK;
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DRM_DEBUG_DRIVER("Calculated GuC WOPCM Region: [%uKiB, %uKiB)\n",
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guc_wopcm_base / 1024, guc_wopcm_size / 1024);
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guc_wopcm_rsvd = GUC_WOPCM_RESERVED + GUC_WOPCM_STACK_RESERVED;
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if ((guc_fw_size + guc_wopcm_rsvd) > guc_wopcm_size) {
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DRM_ERROR("Need %uKiB WOPCM for GuC, %uKiB available.\n",
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(guc_fw_size + guc_wopcm_rsvd) / 1024,
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guc_wopcm_size / 1024);
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return;
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}
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err = check_hw_restriction(i915, guc_wopcm_base, guc_wopcm_size,
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huc_fw_size);
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if (err)
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return;
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wopcm->guc.base = guc_wopcm_base;
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wopcm->guc.size = guc_wopcm_size;
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GEM_BUG_ON(!wopcm->guc.base);
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GEM_BUG_ON(!wopcm->guc.size);
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}
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