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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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cf1c5230ce
This patch converts TILE's architecture-specific 'pcibios_set_master()' routine to a non-inlined function. This will allow follow on patches to create a generic 'pcibios_set_master()' function using the '__weak' attribute which can be used by all architectures as a default which, if necessary, can then be over-ridden by architecture-specific code. Converting 'pci_bios_set_master()' to a non-inlined function will allow TILE's 'pcibios_set_master()' implementation to remain architecture-specific after the generic version is introduced and thus, not change current behavior. No functional change. Acked-by: Chris Metcalf <cmetcalf@tilera.com> Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
98 lines
2.6 KiB
C
98 lines
2.6 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ASM_TILE_PCI_H
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#define _ASM_TILE_PCI_H
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#include <linux/pci.h>
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/*
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* Structure of a PCI controller (host bridge)
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*/
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struct pci_controller {
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int index; /* PCI domain number */
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struct pci_bus *root_bus;
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int first_busno;
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int last_busno;
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int hv_cfg_fd[2]; /* config{0,1} fds for this PCIe controller */
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int hv_mem_fd; /* fd to Hypervisor for MMIO operations */
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struct pci_ops *ops;
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int irq_base; /* Base IRQ from the Hypervisor */
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int plx_gen1; /* flag for PLX Gen 1 configuration */
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/* Address ranges that are routed to this controller/bridge. */
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struct resource mem_resources[3];
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};
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/*
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* The hypervisor maps the entirety of CPA-space as bus addresses, so
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* bus addresses are physical addresses. The networking and block
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* device layers use this boolean for bounce buffer decisions.
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*/
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#define PCI_DMA_BUS_IS_PHYS 1
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int __devinit tile_pci_init(void);
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int __devinit pcibios_init(void);
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void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
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static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
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void __devinit pcibios_fixup_bus(struct pci_bus *bus);
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#define TILE_NUM_PCIE 2
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#define pci_domain_nr(bus) (((struct pci_controller *)(bus)->sysdata)->index)
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/*
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* This decides whether to display the domain number in /proc.
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*/
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static inline int pci_proc_domain(struct pci_bus *bus)
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{
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return 1;
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}
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/*
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* pcibios_assign_all_busses() tells whether or not the bus numbers
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* should be reassigned, in case the BIOS didn't do it correctly, or
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* in case we don't have a BIOS and we want to let Linux do it.
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*/
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static inline int pcibios_assign_all_busses(void)
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{
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return 1;
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}
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#define PCIBIOS_MIN_MEM 0
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#define PCIBIOS_MIN_IO 0
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/*
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* This flag tells if the platform is TILEmpower that needs
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* special configuration for the PLX switch chip.
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*/
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extern int tile_plx_gen1;
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/* Use any cpu for PCI. */
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#define cpumask_of_pcibus(bus) cpu_online_mask
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/* implement the pci_ DMA API in terms of the generic device dma_ one */
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#include <asm-generic/pci-dma-compat.h>
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/* generic pci stuff */
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#include <asm-generic/pci.h>
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#endif /* _ASM_TILE_PCI_H */
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