mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 13:53:54 +07:00
44779b43f1
Move in_suspend flag to adev from gfx, so can be used in other ip blocks, also keep consistent with gpu_in_reset flag. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
363 lines
10 KiB
C
363 lines
10 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_GFX_H__
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#define __AMDGPU_GFX_H__
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/*
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* GFX stuff
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*/
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#include "clearstate_defs.h"
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#include "amdgpu_ring.h"
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/* GFX current status */
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#define AMDGPU_GFX_NORMAL_MODE 0x00000000L
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#define AMDGPU_GFX_SAFE_MODE 0x00000001L
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#define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
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#define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
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#define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
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struct amdgpu_rlc_funcs {
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void (*enter_safe_mode)(struct amdgpu_device *adev);
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void (*exit_safe_mode)(struct amdgpu_device *adev);
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};
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struct amdgpu_rlc {
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/* for power gating */
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struct amdgpu_bo *save_restore_obj;
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uint64_t save_restore_gpu_addr;
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volatile uint32_t *sr_ptr;
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const u32 *reg_list;
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u32 reg_list_size;
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/* for clear state */
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struct amdgpu_bo *clear_state_obj;
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uint64_t clear_state_gpu_addr;
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volatile uint32_t *cs_ptr;
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const struct cs_section_def *cs_data;
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u32 clear_state_size;
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/* for cp tables */
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struct amdgpu_bo *cp_table_obj;
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uint64_t cp_table_gpu_addr;
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volatile uint32_t *cp_table_ptr;
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u32 cp_table_size;
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/* safe mode for updating CG/PG state */
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bool in_safe_mode;
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const struct amdgpu_rlc_funcs *funcs;
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/* for firmware data */
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u32 save_and_restore_offset;
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u32 clear_state_descriptor_offset;
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u32 avail_scratch_ram_locations;
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u32 reg_restore_list_size;
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u32 reg_list_format_start;
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u32 reg_list_format_separate_start;
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u32 starting_offsets_start;
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u32 reg_list_format_size_bytes;
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u32 reg_list_size_bytes;
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u32 reg_list_format_direct_reg_list_length;
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u32 save_restore_list_cntl_size_bytes;
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u32 save_restore_list_gpm_size_bytes;
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u32 save_restore_list_srm_size_bytes;
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u32 *register_list_format;
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u32 *register_restore;
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u8 *save_restore_list_cntl;
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u8 *save_restore_list_gpm;
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u8 *save_restore_list_srm;
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bool is_rlc_v2_1;
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};
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#define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
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struct amdgpu_mec {
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struct amdgpu_bo *hpd_eop_obj;
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u64 hpd_eop_gpu_addr;
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struct amdgpu_bo *mec_fw_obj;
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u64 mec_fw_gpu_addr;
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u32 num_mec;
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u32 num_pipe_per_mec;
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u32 num_queue_per_pipe;
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void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
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/* These are the resources for which amdgpu takes ownership */
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DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
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};
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struct amdgpu_kiq {
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u64 eop_gpu_addr;
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struct amdgpu_bo *eop_obj;
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spinlock_t ring_lock;
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struct amdgpu_ring ring;
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struct amdgpu_irq_src irq;
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};
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/*
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* GPU scratch registers structures, functions & helpers
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*/
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struct amdgpu_scratch {
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unsigned num_reg;
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uint32_t reg_base;
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uint32_t free_mask;
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};
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/*
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* GFX configurations
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*/
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#define AMDGPU_GFX_MAX_SE 4
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#define AMDGPU_GFX_MAX_SH_PER_SE 2
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struct amdgpu_rb_config {
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uint32_t rb_backend_disable;
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uint32_t user_rb_backend_disable;
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uint32_t raster_config;
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uint32_t raster_config_1;
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};
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struct gb_addr_config {
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uint16_t pipe_interleave_size;
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uint8_t num_pipes;
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uint8_t max_compress_frags;
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uint8_t num_banks;
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uint8_t num_se;
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uint8_t num_rb_per_se;
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};
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struct amdgpu_gfx_config {
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unsigned max_shader_engines;
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unsigned max_tile_pipes;
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unsigned max_cu_per_sh;
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unsigned max_sh_per_se;
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unsigned max_backends_per_se;
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unsigned max_texture_channel_caches;
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unsigned max_gprs;
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unsigned max_gs_threads;
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unsigned max_hw_contexts;
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unsigned sc_prim_fifo_size_frontend;
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unsigned sc_prim_fifo_size_backend;
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unsigned sc_hiz_tile_fifo_size;
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unsigned sc_earlyz_tile_fifo_size;
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unsigned num_tile_pipes;
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unsigned backend_enable_mask;
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unsigned mem_max_burst_length_bytes;
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unsigned mem_row_size_in_kb;
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unsigned shader_engine_tile_size;
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unsigned num_gpus;
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unsigned multi_gpu_tile_size;
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unsigned mc_arb_ramcfg;
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unsigned gb_addr_config;
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unsigned num_rbs;
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unsigned gs_vgt_table_depth;
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unsigned gs_prim_buffer_depth;
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uint32_t tile_mode_array[32];
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uint32_t macrotile_mode_array[16];
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struct gb_addr_config gb_addr_config_fields;
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struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
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/* gfx configure feature */
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uint32_t double_offchip_lds_buf;
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/* cached value of DB_DEBUG2 */
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uint32_t db_debug2;
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};
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struct amdgpu_cu_info {
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uint32_t simd_per_cu;
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uint32_t max_waves_per_simd;
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uint32_t wave_front_size;
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uint32_t max_scratch_slots_per_cu;
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uint32_t lds_size;
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/* total active CU number */
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uint32_t number;
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uint32_t ao_cu_mask;
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uint32_t ao_cu_bitmap[4][4];
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uint32_t bitmap[4][4];
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};
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struct amdgpu_gfx_funcs {
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/* get the gpu clock counter */
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uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
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void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num,
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u32 sh_num, u32 instance);
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void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd,
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uint32_t wave, uint32_t *dst, int *no_fields);
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void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd,
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uint32_t wave, uint32_t thread, uint32_t start,
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uint32_t size, uint32_t *dst);
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void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd,
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uint32_t wave, uint32_t start, uint32_t size,
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uint32_t *dst);
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void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe,
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u32 queue);
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};
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struct amdgpu_ngg_buf {
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struct amdgpu_bo *bo;
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uint64_t gpu_addr;
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uint32_t size;
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uint32_t bo_size;
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};
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enum {
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NGG_PRIM = 0,
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NGG_POS,
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NGG_CNTL,
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NGG_PARAM,
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NGG_BUF_MAX
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};
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struct amdgpu_ngg {
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struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
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uint32_t gds_reserve_addr;
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uint32_t gds_reserve_size;
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bool init;
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};
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struct sq_work {
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struct work_struct work;
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unsigned ih_data;
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};
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struct amdgpu_gfx {
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struct mutex gpu_clock_mutex;
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struct amdgpu_gfx_config config;
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struct amdgpu_rlc rlc;
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struct amdgpu_mec mec;
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struct amdgpu_kiq kiq;
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struct amdgpu_scratch scratch;
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const struct firmware *me_fw; /* ME firmware */
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uint32_t me_fw_version;
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const struct firmware *pfp_fw; /* PFP firmware */
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uint32_t pfp_fw_version;
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const struct firmware *ce_fw; /* CE firmware */
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uint32_t ce_fw_version;
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const struct firmware *rlc_fw; /* RLC firmware */
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uint32_t rlc_fw_version;
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const struct firmware *mec_fw; /* MEC firmware */
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uint32_t mec_fw_version;
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const struct firmware *mec2_fw; /* MEC2 firmware */
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uint32_t mec2_fw_version;
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uint32_t me_feature_version;
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uint32_t ce_feature_version;
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uint32_t pfp_feature_version;
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uint32_t rlc_feature_version;
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uint32_t rlc_srlc_fw_version;
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uint32_t rlc_srlc_feature_version;
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uint32_t rlc_srlg_fw_version;
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uint32_t rlc_srlg_feature_version;
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uint32_t rlc_srls_fw_version;
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uint32_t rlc_srls_feature_version;
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uint32_t mec_feature_version;
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uint32_t mec2_feature_version;
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bool mec_fw_write_wait;
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bool me_fw_write_wait;
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struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
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unsigned num_gfx_rings;
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struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
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unsigned num_compute_rings;
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struct amdgpu_irq_src eop_irq;
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struct amdgpu_irq_src priv_reg_irq;
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struct amdgpu_irq_src priv_inst_irq;
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struct amdgpu_irq_src cp_ecc_error_irq;
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struct amdgpu_irq_src sq_irq;
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struct sq_work sq_work;
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/* gfx status */
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uint32_t gfx_current_status;
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/* ce ram size*/
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unsigned ce_ram_size;
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struct amdgpu_cu_info cu_info;
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const struct amdgpu_gfx_funcs *funcs;
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/* reset mask */
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uint32_t grbm_soft_reset;
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uint32_t srbm_soft_reset;
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/* NGG */
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struct amdgpu_ngg ngg;
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/* gfx off */
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bool gfx_off_state; /* true: enabled, false: disabled */
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struct mutex gfx_off_mutex;
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uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */
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struct delayed_work gfx_off_delay_work;
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/* pipe reservation */
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struct mutex pipe_reserve_mutex;
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DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
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};
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#define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
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#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
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#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q))
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/**
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* amdgpu_gfx_create_bitmask - create a bitmask
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*
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* @bit_width: length of the mask
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*
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* create a variable length bit mask.
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* Returns the bitmask.
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*/
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static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
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{
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return (u32)((1ULL << bit_width) - 1);
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}
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int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
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void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
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void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
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unsigned max_sh);
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int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
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struct amdgpu_ring *ring,
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struct amdgpu_irq_src *irq);
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void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
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struct amdgpu_irq_src *irq);
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void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
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int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
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unsigned hpd_size);
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int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev,
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unsigned mqd_size);
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void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev);
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void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
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int amdgpu_gfx_queue_to_bit(struct amdgpu_device *adev, int mec,
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int pipe, int queue);
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void amdgpu_gfx_bit_to_queue(struct amdgpu_device *adev, int bit,
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int *mec, int *pipe, int *queue);
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bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
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int pipe, int queue);
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void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
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#endif
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