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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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55672ecfa2
Detect and recover from machine check when inside opal on a special scom load instructions. On specific SCOM read via MMIO we may get a machine check exception with SRR0 pointing inside opal. To recover from MC in this scenario, get a recovery instruction address and return to it from MC. OPAL will export the machine check recoverable ranges through device tree node mcheck-recoverable-ranges under ibm,opal: # hexdump /proc/device-tree/ibm,opal/mcheck-recoverable-ranges 0000000 0000 0000 3000 2804 0000 000c 0000 0000 0000010 3000 2814 0000 0000 3000 27f0 0000 000c 0000020 0000 0000 3000 2814 xxxx xxxx xxxx xxxx 0000030 llll llll yyyy yyyy yyyy yyyy ... ... # where: xxxx xxxx xxxx xxxx = Starting instruction address llll llll = Length of the address range. yyyy yyyy yyyy yyyy = recovery address Each recoverable address range entry is (start address, len, recovery address), 2 cells each for start and recovery address, 1 cell for len, totalling 5 cells per entry. During kernel boot time, build up the recovery table with the list of recovery ranges from device-tree node which will be used during machine check exception to recover from MMIO SCOM UE. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
353 lines
9.7 KiB
C
353 lines
9.7 KiB
C
/*
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* Machine check exception handling.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright 2013 IBM Corporation
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* Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
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*/
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#undef DEBUG
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#define pr_fmt(fmt) "mce: " fmt
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <linux/percpu.h>
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#include <linux/export.h>
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#include <linux/irq_work.h>
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#include <asm/mce.h>
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static DEFINE_PER_CPU(int, mce_nest_count);
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static DEFINE_PER_CPU(struct machine_check_event[MAX_MC_EVT], mce_event);
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/* Queue for delayed MCE events. */
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static DEFINE_PER_CPU(int, mce_queue_count);
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static DEFINE_PER_CPU(struct machine_check_event[MAX_MC_EVT], mce_event_queue);
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static void machine_check_process_queued_event(struct irq_work *work);
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struct irq_work mce_event_process_work = {
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.func = machine_check_process_queued_event,
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};
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static void mce_set_error_info(struct machine_check_event *mce,
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struct mce_error_info *mce_err)
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{
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mce->error_type = mce_err->error_type;
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switch (mce_err->error_type) {
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case MCE_ERROR_TYPE_UE:
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mce->u.ue_error.ue_error_type = mce_err->u.ue_error_type;
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break;
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case MCE_ERROR_TYPE_SLB:
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mce->u.slb_error.slb_error_type = mce_err->u.slb_error_type;
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break;
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case MCE_ERROR_TYPE_ERAT:
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mce->u.erat_error.erat_error_type = mce_err->u.erat_error_type;
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break;
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case MCE_ERROR_TYPE_TLB:
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mce->u.tlb_error.tlb_error_type = mce_err->u.tlb_error_type;
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break;
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case MCE_ERROR_TYPE_UNKNOWN:
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default:
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break;
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}
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}
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/*
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* Decode and save high level MCE information into per cpu buffer which
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* is an array of machine_check_event structure.
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*/
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void save_mce_event(struct pt_regs *regs, long handled,
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struct mce_error_info *mce_err,
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uint64_t nip, uint64_t addr)
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{
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uint64_t srr1;
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int index = __get_cpu_var(mce_nest_count)++;
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struct machine_check_event *mce = &__get_cpu_var(mce_event[index]);
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/*
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* Return if we don't have enough space to log mce event.
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* mce_nest_count may go beyond MAX_MC_EVT but that's ok,
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* the check below will stop buffer overrun.
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*/
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if (index >= MAX_MC_EVT)
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return;
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/* Populate generic machine check info */
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mce->version = MCE_V1;
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mce->srr0 = nip;
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mce->srr1 = regs->msr;
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mce->gpr3 = regs->gpr[3];
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mce->in_use = 1;
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mce->initiator = MCE_INITIATOR_CPU;
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if (handled)
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mce->disposition = MCE_DISPOSITION_RECOVERED;
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else
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mce->disposition = MCE_DISPOSITION_NOT_RECOVERED;
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mce->severity = MCE_SEV_ERROR_SYNC;
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srr1 = regs->msr;
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/*
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* Populate the mce error_type and type-specific error_type.
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*/
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mce_set_error_info(mce, mce_err);
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if (!addr)
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return;
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if (mce->error_type == MCE_ERROR_TYPE_TLB) {
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mce->u.tlb_error.effective_address_provided = true;
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mce->u.tlb_error.effective_address = addr;
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} else if (mce->error_type == MCE_ERROR_TYPE_SLB) {
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mce->u.slb_error.effective_address_provided = true;
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mce->u.slb_error.effective_address = addr;
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} else if (mce->error_type == MCE_ERROR_TYPE_ERAT) {
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mce->u.erat_error.effective_address_provided = true;
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mce->u.erat_error.effective_address = addr;
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} else if (mce->error_type == MCE_ERROR_TYPE_UE) {
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mce->u.ue_error.effective_address_provided = true;
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mce->u.ue_error.effective_address = addr;
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}
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return;
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}
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/*
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* get_mce_event:
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* mce Pointer to machine_check_event structure to be filled.
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* release Flag to indicate whether to free the event slot or not.
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* 0 <= do not release the mce event. Caller will invoke
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* release_mce_event() once event has been consumed.
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* 1 <= release the slot.
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*
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* return 1 = success
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* 0 = failure
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*
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* get_mce_event() will be called by platform specific machine check
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* handle routine and in KVM.
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* When we call get_mce_event(), we are still in interrupt context and
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* preemption will not be scheduled until ret_from_expect() routine
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* is called.
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*/
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int get_mce_event(struct machine_check_event *mce, bool release)
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{
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int index = __get_cpu_var(mce_nest_count) - 1;
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struct machine_check_event *mc_evt;
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int ret = 0;
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/* Sanity check */
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if (index < 0)
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return ret;
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/* Check if we have MCE info to process. */
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if (index < MAX_MC_EVT) {
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mc_evt = &__get_cpu_var(mce_event[index]);
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/* Copy the event structure and release the original */
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if (mce)
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*mce = *mc_evt;
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if (release)
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mc_evt->in_use = 0;
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ret = 1;
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}
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/* Decrement the count to free the slot. */
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if (release)
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__get_cpu_var(mce_nest_count)--;
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return ret;
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}
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void release_mce_event(void)
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{
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get_mce_event(NULL, true);
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}
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/*
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* Queue up the MCE event which then can be handled later.
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*/
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void machine_check_queue_event(void)
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{
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int index;
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struct machine_check_event evt;
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if (!get_mce_event(&evt, MCE_EVENT_RELEASE))
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return;
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index = __get_cpu_var(mce_queue_count)++;
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/* If queue is full, just return for now. */
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if (index >= MAX_MC_EVT) {
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__get_cpu_var(mce_queue_count)--;
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return;
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}
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__get_cpu_var(mce_event_queue[index]) = evt;
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/* Queue irq work to process this event later. */
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irq_work_queue(&mce_event_process_work);
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}
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/*
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* process pending MCE event from the mce event queue. This function will be
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* called during syscall exit.
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*/
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static void machine_check_process_queued_event(struct irq_work *work)
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{
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int index;
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/*
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* For now just print it to console.
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* TODO: log this error event to FSP or nvram.
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*/
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while (__get_cpu_var(mce_queue_count) > 0) {
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index = __get_cpu_var(mce_queue_count) - 1;
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machine_check_print_event_info(
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&__get_cpu_var(mce_event_queue[index]));
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__get_cpu_var(mce_queue_count)--;
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}
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}
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void machine_check_print_event_info(struct machine_check_event *evt)
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{
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const char *level, *sevstr, *subtype;
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static const char *mc_ue_types[] = {
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"Indeterminate",
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"Instruction fetch",
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"Page table walk ifetch",
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"Load/Store",
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"Page table walk Load/Store",
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};
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static const char *mc_slb_types[] = {
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"Indeterminate",
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"Parity",
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"Multihit",
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};
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static const char *mc_erat_types[] = {
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"Indeterminate",
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"Parity",
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"Multihit",
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};
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static const char *mc_tlb_types[] = {
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"Indeterminate",
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"Parity",
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"Multihit",
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};
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/* Print things out */
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if (evt->version != MCE_V1) {
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pr_err("Machine Check Exception, Unknown event version %d !\n",
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evt->version);
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return;
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}
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switch (evt->severity) {
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case MCE_SEV_NO_ERROR:
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level = KERN_INFO;
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sevstr = "Harmless";
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break;
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case MCE_SEV_WARNING:
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level = KERN_WARNING;
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sevstr = "";
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break;
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case MCE_SEV_ERROR_SYNC:
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level = KERN_ERR;
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sevstr = "Severe";
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break;
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case MCE_SEV_FATAL:
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default:
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level = KERN_ERR;
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sevstr = "Fatal";
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break;
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}
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printk("%s%s Machine check interrupt [%s]\n", level, sevstr,
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evt->disposition == MCE_DISPOSITION_RECOVERED ?
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"Recovered" : "[Not recovered");
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printk("%s Initiator: %s\n", level,
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evt->initiator == MCE_INITIATOR_CPU ? "CPU" : "Unknown");
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switch (evt->error_type) {
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case MCE_ERROR_TYPE_UE:
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subtype = evt->u.ue_error.ue_error_type <
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ARRAY_SIZE(mc_ue_types) ?
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mc_ue_types[evt->u.ue_error.ue_error_type]
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: "Unknown";
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printk("%s Error type: UE [%s]\n", level, subtype);
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if (evt->u.ue_error.effective_address_provided)
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printk("%s Effective address: %016llx\n",
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level, evt->u.ue_error.effective_address);
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if (evt->u.ue_error.physical_address_provided)
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printk("%s Physial address: %016llx\n",
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level, evt->u.ue_error.physical_address);
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break;
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case MCE_ERROR_TYPE_SLB:
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subtype = evt->u.slb_error.slb_error_type <
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ARRAY_SIZE(mc_slb_types) ?
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mc_slb_types[evt->u.slb_error.slb_error_type]
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: "Unknown";
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printk("%s Error type: SLB [%s]\n", level, subtype);
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if (evt->u.slb_error.effective_address_provided)
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printk("%s Effective address: %016llx\n",
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level, evt->u.slb_error.effective_address);
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break;
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case MCE_ERROR_TYPE_ERAT:
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subtype = evt->u.erat_error.erat_error_type <
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ARRAY_SIZE(mc_erat_types) ?
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mc_erat_types[evt->u.erat_error.erat_error_type]
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: "Unknown";
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printk("%s Error type: ERAT [%s]\n", level, subtype);
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if (evt->u.erat_error.effective_address_provided)
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printk("%s Effective address: %016llx\n",
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level, evt->u.erat_error.effective_address);
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break;
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case MCE_ERROR_TYPE_TLB:
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subtype = evt->u.tlb_error.tlb_error_type <
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ARRAY_SIZE(mc_tlb_types) ?
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mc_tlb_types[evt->u.tlb_error.tlb_error_type]
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: "Unknown";
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printk("%s Error type: TLB [%s]\n", level, subtype);
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if (evt->u.tlb_error.effective_address_provided)
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printk("%s Effective address: %016llx\n",
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level, evt->u.tlb_error.effective_address);
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break;
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default:
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case MCE_ERROR_TYPE_UNKNOWN:
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printk("%s Error type: Unknown\n", level);
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break;
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}
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}
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uint64_t get_mce_fault_addr(struct machine_check_event *evt)
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{
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switch (evt->error_type) {
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case MCE_ERROR_TYPE_UE:
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if (evt->u.ue_error.effective_address_provided)
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return evt->u.ue_error.effective_address;
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break;
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case MCE_ERROR_TYPE_SLB:
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if (evt->u.slb_error.effective_address_provided)
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return evt->u.slb_error.effective_address;
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break;
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case MCE_ERROR_TYPE_ERAT:
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if (evt->u.erat_error.effective_address_provided)
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return evt->u.erat_error.effective_address;
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break;
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case MCE_ERROR_TYPE_TLB:
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if (evt->u.tlb_error.effective_address_provided)
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return evt->u.tlb_error.effective_address;
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break;
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default:
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case MCE_ERROR_TYPE_UNKNOWN:
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break;
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}
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return 0;
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}
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EXPORT_SYMBOL(get_mce_fault_addr);
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