mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 18:56:40 +07:00
237865f195
Revertdff22d2054
("PCI: Call pci_read_bridge_bases() from core instead of arch code"). Reading PCI bridge windows is not arch-specific in itself, but there is PCI core code that doesn't work correctly if we read them too early. For example, Hannes found this case on an ARM Freescale i.mx6 board: pci_bus 0000:00: root bus resource [mem 0x01000000-0x01efffff] pci 0000:00:00.0: PCI bridge to [bus 01-ff] pci 0000:00:00.0: BAR 8: no space for [mem size 0x01000000] (mem window) pci 0000:01:00.0: BAR 2: failed to assign [mem size 0x00200000] pci 0000:01:00.0: BAR 1: failed to assign [mem size 0x00004000] pci 0000:01:00.0: BAR 0: failed to assign [mem size 0x00000100] The 00:00.0 mem window needs to be at least 3MB: the 01:00.0 device needs 0x204100 of space, and mem windows are megabyte-aligned. Bus sizing can increase a bridge window size, but never *decrease* it (seed65245c329
("PCI: don't shrink bridge resources")). Prior todff22d2054
, ARM didn't read bridge windows at all, so the "original size" was zero, and we assigned a 3MB window. Afterdff22d2054
, we read the bridge windows before sizing the bus. The firmware programmed a 16MB window (size 0x01000000) in 00:00.0, and since we never decrease the size, we kept 16MB even though we only needed 3MB. But 16MB doesn't fit in the host bridge aperture, so we failed to assign space for the window and the downstream devices. I think this is a defect in the PCI core: we shouldn't rely on the firmware to assign sensible windows. Ray reported a similar problem, also on ARM, with Broadcom iProc. Issues like this are too hard to fix right now, so revertdff22d2054
. Reported-by: Hannes <oe5hpm@gmail.com> Reported-by: Ray Jui <rjui@broadcom.com> Link: http://lkml.kernel.org/r/CAAa04yFQEUJm7Jj1qMT57-LG7ZGtnhNDBe=PpSRa70Mj+XhW-A@mail.gmail.com Link: http://lkml.kernel.org/r/55F75BB8.4070405@broadcom.com Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Yinghai Lu <yinghai@kernel.org> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
357 lines
8.5 KiB
C
357 lines
8.5 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2011 Wind River Systems,
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* written by Ralf Baechle (ralf@linux-mips.org)
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*/
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#include <linux/bug.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/bootmem.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/of_address.h>
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#include <asm/cpu-info.h>
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/*
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* If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
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* assignments.
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*/
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/*
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* The PCI controller list.
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*/
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static struct pci_controller *hose_head, **hose_tail = &hose_head;
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unsigned long PCIBIOS_MIN_IO;
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unsigned long PCIBIOS_MIN_MEM;
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static int pci_initialized;
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/*
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* We need to avoid collisions with `mirrored' VGA ports
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* and other strange ISA hardware, so we always want the
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* addresses to be allocated in the 0x000-0x0ff region
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* modulo 0x400.
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*
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* Why? Because some silly external IO cards only decode
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* the low 10 bits of the IO address. The 0x00-0xff region
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* is reserved for motherboard devices that decode all 16
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* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
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* but we want to try to avoid allocating at 0x2900-0x2bff
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* which might have be mirrored at 0x0100-0x03ff..
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*/
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resource_size_t
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pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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struct pci_dev *dev = data;
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struct pci_controller *hose = dev->sysdata;
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resource_size_t start = res->start;
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if (res->flags & IORESOURCE_IO) {
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/* Make sure we start at our min on all hoses */
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if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
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start = PCIBIOS_MIN_IO + hose->io_resource->start;
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/*
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* Put everything into 0x00-0xff region modulo 0x400
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*/
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if (start & 0x300)
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start = (start + 0x3ff) & ~0x3ff;
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} else if (res->flags & IORESOURCE_MEM) {
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/* Make sure we start at our min on all hoses */
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if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
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start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
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}
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return start;
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}
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static void pcibios_scanbus(struct pci_controller *hose)
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{
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static int next_busno;
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static int need_domain_info;
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LIST_HEAD(resources);
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struct pci_bus *bus;
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if (!hose->iommu)
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PCI_DMA_BUS_IS_PHYS = 1;
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if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
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next_busno = (*hose->get_busno)();
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pci_add_resource_offset(&resources,
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hose->mem_resource, hose->mem_offset);
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pci_add_resource_offset(&resources,
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hose->io_resource, hose->io_offset);
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pci_add_resource_offset(&resources,
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hose->busn_resource, hose->busn_offset);
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bus = pci_scan_root_bus(NULL, next_busno, hose->pci_ops, hose,
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&resources);
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hose->bus = bus;
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need_domain_info = need_domain_info || hose->index;
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hose->need_domain_info = need_domain_info;
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if (!bus) {
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pci_free_resource_list(&resources);
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return;
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}
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next_busno = bus->busn_res.end + 1;
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/* Don't allow 8-bit bus number overflow inside the hose -
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reserve some space for bridges. */
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if (next_busno > 224) {
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next_busno = 0;
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need_domain_info = 1;
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}
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if (!pci_has_flag(PCI_PROBE_ONLY)) {
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pci_bus_size_bridges(bus);
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pci_bus_assign_resources(bus);
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}
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pci_bus_add_devices(bus);
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}
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#ifdef CONFIG_OF
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void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
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{
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struct of_pci_range range;
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struct of_pci_range_parser parser;
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pr_info("PCI host bridge %s ranges:\n", node->full_name);
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hose->of_node = node;
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if (of_pci_range_parser_init(&parser, node))
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return;
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for_each_of_pci_range(&parser, &range) {
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struct resource *res = NULL;
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switch (range.flags & IORESOURCE_TYPE_BITS) {
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case IORESOURCE_IO:
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pr_info(" IO 0x%016llx..0x%016llx\n",
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range.cpu_addr,
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range.cpu_addr + range.size - 1);
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hose->io_map_base =
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(unsigned long)ioremap(range.cpu_addr,
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range.size);
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res = hose->io_resource;
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break;
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case IORESOURCE_MEM:
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pr_info(" MEM 0x%016llx..0x%016llx\n",
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range.cpu_addr,
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range.cpu_addr + range.size - 1);
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res = hose->mem_resource;
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break;
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}
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if (res != NULL)
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of_pci_range_to_resource(&range, node, res);
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}
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}
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struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
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{
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struct pci_controller *hose = bus->sysdata;
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return of_node_get(hose->of_node);
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}
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#endif
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static DEFINE_MUTEX(pci_scan_mutex);
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void register_pci_controller(struct pci_controller *hose)
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{
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struct resource *parent;
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parent = hose->mem_resource->parent;
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if (!parent)
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parent = &iomem_resource;
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if (request_resource(parent, hose->mem_resource) < 0)
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goto out;
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parent = hose->io_resource->parent;
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if (!parent)
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parent = &ioport_resource;
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if (request_resource(parent, hose->io_resource) < 0) {
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release_resource(hose->mem_resource);
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goto out;
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}
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*hose_tail = hose;
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hose_tail = &hose->next;
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/*
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* Do not panic here but later - this might happen before console init.
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*/
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if (!hose->io_map_base) {
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printk(KERN_WARNING
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"registering PCI controller with io_map_base unset\n");
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}
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/*
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* Scan the bus if it is register after the PCI subsystem
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* initialization.
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*/
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if (pci_initialized) {
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mutex_lock(&pci_scan_mutex);
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pcibios_scanbus(hose);
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mutex_unlock(&pci_scan_mutex);
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}
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return;
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out:
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printk(KERN_WARNING
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"Skipping PCI bus scan due to resource conflict\n");
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}
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static void __init pcibios_set_cache_line_size(void)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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unsigned int lsize;
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/*
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* Set PCI cacheline size to that of the highest level in the
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* cache hierarchy.
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*/
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lsize = c->dcache.linesz;
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lsize = c->scache.linesz ? : lsize;
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lsize = c->tcache.linesz ? : lsize;
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BUG_ON(!lsize);
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pci_dfl_cache_line_size = lsize >> 2;
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pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
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}
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static int __init pcibios_init(void)
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{
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struct pci_controller *hose;
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pcibios_set_cache_line_size();
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/* Scan all of the recorded PCI controllers. */
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for (hose = hose_head; hose; hose = hose->next)
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pcibios_scanbus(hose);
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pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq);
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pci_initialized = 1;
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return 0;
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}
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subsys_initcall(pcibios_init);
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static int pcibios_enable_resources(struct pci_dev *dev, int mask)
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{
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u16 cmd, old_cmd;
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int idx;
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struct resource *r;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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old_cmd = cmd;
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for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
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/* Only set up the requested stuff */
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if (!(mask & (1<<idx)))
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continue;
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r = &dev->resource[idx];
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if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
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continue;
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if ((idx == PCI_ROM_RESOURCE) &&
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(!(r->flags & IORESOURCE_ROM_ENABLE)))
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continue;
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if (!r->start && r->end) {
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printk(KERN_ERR "PCI: Device %s not available "
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"because of resource collisions\n",
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pci_name(dev));
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return -EINVAL;
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}
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if (r->flags & IORESOURCE_IO)
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cmd |= PCI_COMMAND_IO;
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if (r->flags & IORESOURCE_MEM)
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cmd |= PCI_COMMAND_MEMORY;
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}
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if (cmd != old_cmd) {
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printk("PCI: Enabling device %s (%04x -> %04x)\n",
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pci_name(dev), old_cmd, cmd);
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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}
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return 0;
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}
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unsigned int pcibios_assign_all_busses(void)
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{
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return 1;
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}
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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int err;
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if ((err = pcibios_enable_resources(dev, mask)) < 0)
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return err;
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return pcibios_plat_dev_init(dev);
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}
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void pcibios_fixup_bus(struct pci_bus *bus)
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{
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struct pci_dev *dev = bus->self;
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if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
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(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
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pci_read_bridge_bases(bus);
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}
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}
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EXPORT_SYMBOL(PCIBIOS_MIN_IO);
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EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
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int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine)
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{
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unsigned long prot;
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/*
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* I/O space can be accessed via normal processor loads and stores on
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* this platform but for now we elect not to do this and portable
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* drivers should not do this anyway.
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*/
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if (mmap_state == pci_mmap_io)
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return -EINVAL;
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/*
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* Ignore write-combine; for now only return uncached mappings.
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*/
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prot = pgprot_val(vma->vm_page_prot);
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prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
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vma->vm_page_prot = __pgprot(prot);
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return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
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vma->vm_end - vma->vm_start, vma->vm_page_prot);
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}
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char * (*pcibios_plat_setup)(char *str) __initdata;
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char *__init pcibios_setup(char *str)
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{
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if (pcibios_plat_setup)
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return pcibios_plat_setup(str);
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return str;
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}
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