mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-08 15:56:40 +07:00
325f0a1833
Update mips/netlogic/common/irq.c and mips/pci/msi-xlp.c to use chip_data to store interrupt controller data pointer. It uses handler_data now, and that causes errors when an API (like the GPIO subsystem) tries to use the handler data. Signed-off-by: Kamlakant Patel <kamlakant.patel@broadcom.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10817/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
572 lines
16 KiB
C
572 lines
16 KiB
C
/*
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the Broadcom
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/msi.h>
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#include <linux/mm.h>
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#include <linux/irq.h>
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#include <linux/irqdesc.h>
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#include <linux/console.h>
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#include <asm/io.h>
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#include <asm/netlogic/interrupt.h>
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/common.h>
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#include <asm/netlogic/mips-extns.h>
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/pic.h>
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#include <asm/netlogic/xlp-hal/pcibus.h>
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#include <asm/netlogic/xlp-hal/bridge.h>
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#define XLP_MSIVEC_PER_LINK 32
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#define XLP_MSIXVEC_TOTAL (cpu_is_xlp9xx() ? 128 : 32)
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#define XLP_MSIXVEC_PER_LINK (cpu_is_xlp9xx() ? 32 : 8)
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/* 128 MSI irqs per node, mapped starting at NLM_MSI_VEC_BASE */
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static inline int nlm_link_msiirq(int link, int msivec)
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{
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return NLM_MSI_VEC_BASE + link * XLP_MSIVEC_PER_LINK + msivec;
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}
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/* get the link MSI vector from irq number */
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static inline int nlm_irq_msivec(int irq)
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{
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return (irq - NLM_MSI_VEC_BASE) % XLP_MSIVEC_PER_LINK;
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}
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/* get the link from the irq number */
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static inline int nlm_irq_msilink(int irq)
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{
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int total_msivec = XLP_MSIVEC_PER_LINK * PCIE_NLINKS;
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return ((irq - NLM_MSI_VEC_BASE) % total_msivec) /
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XLP_MSIVEC_PER_LINK;
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}
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/*
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* For XLP 8xx/4xx/3xx/2xx, only 32 MSI-X vectors are possible because
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* there are only 32 PIC interrupts for MSI. We split them statically
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* and use 8 MSI-X vectors per link - this keeps the allocation and
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* lookup simple.
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* On XLP 9xx, there are 32 vectors per link, and the interrupts are
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* not routed thru PIC, so we can use all 128 MSI-X vectors.
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*/
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static inline int nlm_link_msixirq(int link, int bit)
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{
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return NLM_MSIX_VEC_BASE + link * XLP_MSIXVEC_PER_LINK + bit;
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}
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/* get the link MSI vector from irq number */
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static inline int nlm_irq_msixvec(int irq)
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{
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return (irq - NLM_MSIX_VEC_BASE) % XLP_MSIXVEC_TOTAL;
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}
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/* get the link from MSIX vec */
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static inline int nlm_irq_msixlink(int msixvec)
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{
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return msixvec / XLP_MSIXVEC_PER_LINK;
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}
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/*
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* Per link MSI and MSI-X information, set as IRQ handler data for
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* MSI and MSI-X interrupts.
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*/
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struct xlp_msi_data {
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struct nlm_soc_info *node;
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uint64_t lnkbase;
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uint32_t msi_enabled_mask;
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uint32_t msi_alloc_mask;
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uint32_t msix_alloc_mask;
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spinlock_t msi_lock;
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};
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/*
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* MSI Chip definitions
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*
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* On XLP, there is a PIC interrupt associated with each PCIe link on the
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* chip (which appears as a PCI bridge to us). This gives us 32 MSI irqa
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* per link and 128 overall.
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*
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* When a device connected to the link raises a MSI interrupt, we get a
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* link interrupt and we then have to look at PCIE_MSI_STATUS register at
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* the bridge to map it to the IRQ
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*/
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static void xlp_msi_enable(struct irq_data *d)
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{
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struct xlp_msi_data *md = irq_data_get_irq_chip_data(d);
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unsigned long flags;
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int vec;
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vec = nlm_irq_msivec(d->irq);
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spin_lock_irqsave(&md->msi_lock, flags);
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md->msi_enabled_mask |= 1u << vec;
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if (cpu_is_xlp9xx())
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nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_EN,
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md->msi_enabled_mask);
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else
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nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask);
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spin_unlock_irqrestore(&md->msi_lock, flags);
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}
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static void xlp_msi_disable(struct irq_data *d)
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{
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struct xlp_msi_data *md = irq_data_get_irq_chip_data(d);
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unsigned long flags;
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int vec;
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vec = nlm_irq_msivec(d->irq);
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spin_lock_irqsave(&md->msi_lock, flags);
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md->msi_enabled_mask &= ~(1u << vec);
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if (cpu_is_xlp9xx())
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nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_EN,
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md->msi_enabled_mask);
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else
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nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask);
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spin_unlock_irqrestore(&md->msi_lock, flags);
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}
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static void xlp_msi_mask_ack(struct irq_data *d)
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{
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struct xlp_msi_data *md = irq_data_get_irq_chip_data(d);
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int link, vec;
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link = nlm_irq_msilink(d->irq);
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vec = nlm_irq_msivec(d->irq);
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xlp_msi_disable(d);
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/* Ack MSI on bridge */
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if (cpu_is_xlp9xx())
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nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_STATUS, 1u << vec);
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else
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nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec);
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}
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static struct irq_chip xlp_msi_chip = {
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.name = "XLP-MSI",
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.irq_enable = xlp_msi_enable,
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.irq_disable = xlp_msi_disable,
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.irq_mask_ack = xlp_msi_mask_ack,
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.irq_unmask = xlp_msi_enable,
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};
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/*
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* XLP8XX/4XX/3XX/2XX:
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* The MSI-X interrupt handling is different from MSI, there are 32 MSI-X
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* interrupts generated by the PIC and each of these correspond to a MSI-X
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* vector (0-31) that can be assigned.
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*
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* We divide the MSI-X vectors to 8 per link and do a per-link allocation
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*
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* XLP9XX:
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* 32 MSI-X vectors are available per link, and the interrupts are not routed
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* thru the PIC. PIC ack not needed.
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*
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* Enable and disable done using standard MSI functions.
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*/
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static void xlp_msix_mask_ack(struct irq_data *d)
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{
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struct xlp_msi_data *md;
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int link, msixvec;
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uint32_t status_reg, bit;
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msixvec = nlm_irq_msixvec(d->irq);
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link = nlm_irq_msixlink(msixvec);
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pci_msi_mask_irq(d);
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md = irq_data_get_irq_chip_data(d);
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/* Ack MSI on bridge */
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if (cpu_is_xlp9xx()) {
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status_reg = PCIE_9XX_MSIX_STATUSX(link);
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bit = msixvec % XLP_MSIXVEC_PER_LINK;
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} else {
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status_reg = PCIE_MSIX_STATUS;
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bit = msixvec;
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}
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nlm_write_reg(md->lnkbase, status_reg, 1u << bit);
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if (!cpu_is_xlp9xx())
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nlm_pic_ack(md->node->picbase,
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PIC_IRT_PCIE_MSIX_INDEX(msixvec));
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}
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static struct irq_chip xlp_msix_chip = {
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.name = "XLP-MSIX",
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.irq_enable = pci_msi_unmask_irq,
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.irq_disable = pci_msi_mask_irq,
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.irq_mask_ack = xlp_msix_mask_ack,
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.irq_unmask = pci_msi_unmask_irq,
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};
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void arch_teardown_msi_irq(unsigned int irq)
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{
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}
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/*
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* Setup a PCIe link for MSI. By default, the links are in
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* legacy interrupt mode. We will switch them to MSI mode
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* at the first MSI request.
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*/
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static void xlp_config_link_msi(uint64_t lnkbase, int lirq, uint64_t msiaddr)
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{
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u32 val;
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if (cpu_is_xlp9xx()) {
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val = nlm_read_reg(lnkbase, PCIE_9XX_INT_EN0);
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if ((val & 0x200) == 0) {
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val |= 0x200; /* MSI Interrupt enable */
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nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val);
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}
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} else {
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val = nlm_read_reg(lnkbase, PCIE_INT_EN0);
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if ((val & 0x200) == 0) {
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val |= 0x200;
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nlm_write_reg(lnkbase, PCIE_INT_EN0, val);
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}
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}
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val = nlm_read_reg(lnkbase, 0x1); /* CMD */
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if ((val & 0x0400) == 0) {
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val |= 0x0400;
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nlm_write_reg(lnkbase, 0x1, val);
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}
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/* Update IRQ in the PCI irq reg */
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val = nlm_read_pci_reg(lnkbase, 0xf);
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val &= ~0x1fu;
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val |= (1 << 8) | lirq;
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nlm_write_pci_reg(lnkbase, 0xf, val);
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/* MSI addr */
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nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRH, msiaddr >> 32);
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nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRL, msiaddr & 0xffffffff);
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/* MSI cap for bridge */
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val = nlm_read_reg(lnkbase, PCIE_BRIDGE_MSI_CAP);
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if ((val & (1 << 16)) == 0) {
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val |= 0xb << 16; /* mmc32, msi enable */
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nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_CAP, val);
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}
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}
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/*
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* Allocate a MSI vector on a link
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*/
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static int xlp_setup_msi(uint64_t lnkbase, int node, int link,
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struct msi_desc *desc)
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{
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struct xlp_msi_data *md;
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struct msi_msg msg;
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unsigned long flags;
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int msivec, irt, lirq, xirq, ret;
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uint64_t msiaddr;
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/* Get MSI data for the link */
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lirq = PIC_PCIE_LINK_MSI_IRQ(link);
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xirq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
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md = irq_get_chip_data(xirq);
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msiaddr = MSI_LINK_ADDR(node, link);
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spin_lock_irqsave(&md->msi_lock, flags);
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if (md->msi_alloc_mask == 0) {
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xlp_config_link_msi(lnkbase, lirq, msiaddr);
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/* switch the link IRQ to MSI range */
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if (cpu_is_xlp9xx())
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irt = PIC_9XX_IRT_PCIE_LINK_INDEX(link);
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else
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irt = PIC_IRT_PCIE_LINK_INDEX(link);
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nlm_setup_pic_irq(node, lirq, lirq, irt);
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nlm_pic_init_irt(nlm_get_node(node)->picbase, irt, lirq,
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node * nlm_threads_per_node(), 1 /*en */);
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}
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/* allocate a MSI vec, and tell the bridge about it */
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msivec = fls(md->msi_alloc_mask);
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if (msivec == XLP_MSIVEC_PER_LINK) {
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spin_unlock_irqrestore(&md->msi_lock, flags);
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return -ENOMEM;
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}
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md->msi_alloc_mask |= (1u << msivec);
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spin_unlock_irqrestore(&md->msi_lock, flags);
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msg.address_hi = msiaddr >> 32;
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msg.address_lo = msiaddr & 0xffffffff;
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msg.data = 0xc00 | msivec;
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xirq = xirq + msivec; /* msi mapped to global irq space */
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ret = irq_set_msi_desc(xirq, desc);
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if (ret < 0)
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return ret;
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pci_write_msi_msg(xirq, &msg);
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return 0;
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}
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/*
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* Switch a link to MSI-X mode
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*/
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static void xlp_config_link_msix(uint64_t lnkbase, int lirq, uint64_t msixaddr)
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{
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u32 val;
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val = nlm_read_reg(lnkbase, 0x2C);
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if ((val & 0x80000000U) == 0) {
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val |= 0x80000000U;
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nlm_write_reg(lnkbase, 0x2C, val);
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}
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if (cpu_is_xlp9xx()) {
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val = nlm_read_reg(lnkbase, PCIE_9XX_INT_EN0);
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if ((val & 0x200) == 0) {
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val |= 0x200; /* MSI Interrupt enable */
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nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val);
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}
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} else {
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val = nlm_read_reg(lnkbase, PCIE_INT_EN0);
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if ((val & 0x200) == 0) {
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val |= 0x200; /* MSI Interrupt enable */
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nlm_write_reg(lnkbase, PCIE_INT_EN0, val);
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}
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}
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val = nlm_read_reg(lnkbase, 0x1); /* CMD */
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if ((val & 0x0400) == 0) {
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val |= 0x0400;
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nlm_write_reg(lnkbase, 0x1, val);
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}
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/* Update IRQ in the PCI irq reg */
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val = nlm_read_pci_reg(lnkbase, 0xf);
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val &= ~0x1fu;
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val |= (1 << 8) | lirq;
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nlm_write_pci_reg(lnkbase, 0xf, val);
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if (cpu_is_xlp9xx()) {
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/* MSI-X addresses */
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nlm_write_reg(lnkbase, PCIE_9XX_BRIDGE_MSIX_ADDR_BASE,
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msixaddr >> 8);
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nlm_write_reg(lnkbase, PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT,
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(msixaddr + MSI_ADDR_SZ) >> 8);
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} else {
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/* MSI-X addresses */
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nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_BASE,
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msixaddr >> 8);
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nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_LIMIT,
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(msixaddr + MSI_ADDR_SZ) >> 8);
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}
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}
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/*
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* Allocate a MSI-X vector
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*/
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static int xlp_setup_msix(uint64_t lnkbase, int node, int link,
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struct msi_desc *desc)
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{
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struct xlp_msi_data *md;
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struct msi_msg msg;
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unsigned long flags;
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int t, msixvec, lirq, xirq, ret;
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uint64_t msixaddr;
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/* Get MSI data for the link */
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lirq = PIC_PCIE_MSIX_IRQ(link);
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xirq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0));
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md = irq_get_chip_data(xirq);
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msixaddr = MSIX_LINK_ADDR(node, link);
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spin_lock_irqsave(&md->msi_lock, flags);
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/* switch the PCIe link to MSI-X mode at the first alloc */
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if (md->msix_alloc_mask == 0)
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xlp_config_link_msix(lnkbase, lirq, msixaddr);
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/* allocate a MSI-X vec, and tell the bridge about it */
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t = fls(md->msix_alloc_mask);
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if (t == XLP_MSIXVEC_PER_LINK) {
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spin_unlock_irqrestore(&md->msi_lock, flags);
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return -ENOMEM;
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}
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md->msix_alloc_mask |= (1u << t);
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spin_unlock_irqrestore(&md->msi_lock, flags);
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xirq += t;
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msixvec = nlm_irq_msixvec(xirq);
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msg.address_hi = msixaddr >> 32;
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msg.address_lo = msixaddr & 0xffffffff;
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msg.data = 0xc00 | msixvec;
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ret = irq_set_msi_desc(xirq, desc);
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if (ret < 0)
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return ret;
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pci_write_msi_msg(xirq, &msg);
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return 0;
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}
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int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
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{
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struct pci_dev *lnkdev;
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uint64_t lnkbase;
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int node, link, slot;
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lnkdev = xlp_get_pcie_link(dev);
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if (lnkdev == NULL) {
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dev_err(&dev->dev, "Could not find bridge\n");
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return 1;
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}
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slot = PCI_SLOT(lnkdev->devfn);
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link = PCI_FUNC(lnkdev->devfn);
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node = slot / 8;
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lnkbase = nlm_get_pcie_base(node, link);
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if (desc->msi_attrib.is_msix)
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return xlp_setup_msix(lnkbase, node, link, desc);
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else
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return xlp_setup_msi(lnkbase, node, link, desc);
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}
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void __init xlp_init_node_msi_irqs(int node, int link)
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{
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struct nlm_soc_info *nodep;
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struct xlp_msi_data *md;
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int irq, i, irt, msixvec, val;
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pr_info("[%d %d] Init node PCI IRT\n", node, link);
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nodep = nlm_get_node(node);
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/* Alloc an MSI block for the link */
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md = kzalloc(sizeof(*md), GFP_KERNEL);
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spin_lock_init(&md->msi_lock);
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md->msi_enabled_mask = 0;
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md->msi_alloc_mask = 0;
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md->msix_alloc_mask = 0;
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md->node = nodep;
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md->lnkbase = nlm_get_pcie_base(node, link);
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|
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/* extended space for MSI interrupts */
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irq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
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for (i = irq; i < irq + XLP_MSIVEC_PER_LINK; i++) {
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irq_set_chip_and_handler(i, &xlp_msi_chip, handle_level_irq);
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irq_set_chip_data(i, md);
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}
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|
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for (i = 0; i < XLP_MSIXVEC_PER_LINK ; i++) {
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if (cpu_is_xlp9xx()) {
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val = ((node * nlm_threads_per_node()) << 7 |
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PIC_PCIE_MSIX_IRQ(link) << 1 | 0 << 0);
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nlm_write_pcie_reg(md->lnkbase, PCIE_9XX_MSIX_VECX(i +
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(link * XLP_MSIXVEC_PER_LINK)), val);
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} else {
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/* Initialize MSI-X irts to generate one interrupt
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* per link
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|
*/
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msixvec = link * XLP_MSIXVEC_PER_LINK + i;
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irt = PIC_IRT_PCIE_MSIX_INDEX(msixvec);
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nlm_pic_init_irt(nodep->picbase, irt,
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PIC_PCIE_MSIX_IRQ(link),
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node * nlm_threads_per_node(), 1);
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}
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|
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/* Initialize MSI-X extended irq space for the link */
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irq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, i));
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irq_set_chip_and_handler(irq, &xlp_msix_chip, handle_level_irq);
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irq_set_chip_data(irq, md);
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}
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}
|
|
|
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void nlm_dispatch_msi(int node, int lirq)
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|
{
|
|
struct xlp_msi_data *md;
|
|
int link, i, irqbase;
|
|
u32 status;
|
|
|
|
link = lirq - PIC_PCIE_LINK_MSI_IRQ_BASE;
|
|
irqbase = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0));
|
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md = irq_get_chip_data(irqbase);
|
|
if (cpu_is_xlp9xx())
|
|
status = nlm_read_reg(md->lnkbase, PCIE_9XX_MSI_STATUS) &
|
|
md->msi_enabled_mask;
|
|
else
|
|
status = nlm_read_reg(md->lnkbase, PCIE_MSI_STATUS) &
|
|
md->msi_enabled_mask;
|
|
while (status) {
|
|
i = __ffs(status);
|
|
do_IRQ(irqbase + i);
|
|
status &= status - 1;
|
|
}
|
|
|
|
/* Ack at eirr and PIC */
|
|
ack_c0_eirr(PIC_PCIE_LINK_MSI_IRQ(link));
|
|
if (cpu_is_xlp9xx())
|
|
nlm_pic_ack(md->node->picbase,
|
|
PIC_9XX_IRT_PCIE_LINK_INDEX(link));
|
|
else
|
|
nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link));
|
|
}
|
|
|
|
void nlm_dispatch_msix(int node, int lirq)
|
|
{
|
|
struct xlp_msi_data *md;
|
|
int link, i, irqbase;
|
|
u32 status;
|
|
|
|
link = lirq - PIC_PCIE_MSIX_IRQ_BASE;
|
|
irqbase = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0));
|
|
md = irq_get_chip_data(irqbase);
|
|
if (cpu_is_xlp9xx())
|
|
status = nlm_read_reg(md->lnkbase, PCIE_9XX_MSIX_STATUSX(link));
|
|
else
|
|
status = nlm_read_reg(md->lnkbase, PCIE_MSIX_STATUS);
|
|
|
|
/* narrow it down to the MSI-x vectors for our link */
|
|
if (!cpu_is_xlp9xx())
|
|
status = (status >> (link * XLP_MSIXVEC_PER_LINK)) &
|
|
((1 << XLP_MSIXVEC_PER_LINK) - 1);
|
|
|
|
while (status) {
|
|
i = __ffs(status);
|
|
do_IRQ(irqbase + i);
|
|
status &= status - 1;
|
|
}
|
|
/* Ack at eirr and PIC */
|
|
ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link));
|
|
}
|