mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 23:46:42 +07:00
bd0b9ac405
Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com>
166 lines
3.5 KiB
C
166 lines
3.5 KiB
C
/*
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* arch/arm/mach-iop13xx/msi.c
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*
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* PCI MSI support for the iop13xx processor
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*
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* Copyright (c) 2006, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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*/
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#include <linux/pci.h>
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#include <linux/msi.h>
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#include <asm/mach/irq.h>
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#include <asm/irq.h>
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#include <mach/irqs.h>
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/* IMIPR0 CP6 R8 Page 1
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*/
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static u32 read_imipr_0(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val));
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return val;
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}
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static void write_imipr_0(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val));
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}
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/* IMIPR1 CP6 R9 Page 1
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*/
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static u32 read_imipr_1(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val));
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return val;
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}
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static void write_imipr_1(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val));
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}
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/* IMIPR2 CP6 R10 Page 1
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*/
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static u32 read_imipr_2(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val));
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return val;
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}
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static void write_imipr_2(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val));
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}
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/* IMIPR3 CP6 R11 Page 1
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*/
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static u32 read_imipr_3(void)
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{
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u32 val;
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asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val));
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return val;
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}
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static void write_imipr_3(u32 val)
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{
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asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val));
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}
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static u32 (*read_imipr[])(void) = {
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read_imipr_0,
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read_imipr_1,
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read_imipr_2,
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read_imipr_3,
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};
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static void (*write_imipr[])(u32) = {
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write_imipr_0,
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write_imipr_1,
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write_imipr_2,
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write_imipr_3,
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};
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static void iop13xx_msi_handler(struct irq_desc *desc)
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{
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int i, j;
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unsigned long status;
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/* read IMIPR registers and find any active interrupts,
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* then call ISR for each active interrupt
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*/
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for (i = 0; i < ARRAY_SIZE(read_imipr); i++) {
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status = (read_imipr[i])();
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if (!status)
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continue;
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do {
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j = find_first_bit(&status, 32);
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(write_imipr[i])(1 << j); /* write back to clear bit */
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generic_handle_irq(IRQ_IOP13XX_MSI_0 + j + (32*i));
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status = (read_imipr[i])();
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} while (status);
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}
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}
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void __init iop13xx_msi_init(void)
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{
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irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler);
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}
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static void iop13xx_msi_nop(struct irq_data *d)
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{
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return;
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}
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static struct irq_chip iop13xx_msi_chip = {
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.name = "PCI-MSI",
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.irq_ack = iop13xx_msi_nop,
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.irq_enable = pci_msi_unmask_irq,
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.irq_disable = pci_msi_mask_irq,
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.irq_mask = pci_msi_mask_irq,
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.irq_unmask = pci_msi_unmask_irq,
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};
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int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
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{
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int id, irq = irq_alloc_desc_from(IRQ_IOP13XX_MSI_0, -1);
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struct msi_msg msg;
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if (irq < 0)
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return irq;
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if (irq >= NR_IOP13XX_IRQS) {
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irq_free_desc(irq);
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return -ENOSPC;
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}
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irq_set_msi_desc(irq, desc);
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msg.address_hi = 0x0;
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msg.address_lo = IOP13XX_MU_MIMR_PCI;
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id = iop13xx_cpu_id();
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msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f);
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pci_write_msi_msg(irq, &msg);
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irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
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return 0;
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}
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void arch_teardown_msi_irq(unsigned int irq)
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{
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irq_free_desc(irq);
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}
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