mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-11 04:36:40 +07:00
8423536fe4
Move the selection of the pinctrl driver to SoC family level since we have two pinctrl drivers. It is useless to select one which is not compatible with the SoC. [abelloni: fixed pm.c when only sama2d2 is selected] Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
453 lines
11 KiB
C
453 lines
11 KiB
C
/*
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* arch/arm/mach-at91/pm.c
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* AT91 Power Management
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*
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* Copyright (C) 2005 David Brownell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/gpio.h>
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#include <linux/suspend.h>
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#include <linux/sched.h>
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#include <linux/proc_fs.h>
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#include <linux/genalloc.h>
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#include <linux/interrupt.h>
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#include <linux/sysfs.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/clk/at91_pmc.h>
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#include <asm/irq.h>
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#include <linux/atomic.h>
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#include <asm/mach/time.h>
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#include <asm/mach/irq.h>
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#include <asm/fncpy.h>
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#include <asm/cacheflush.h>
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#include "generic.h"
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#include "pm.h"
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/*
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* FIXME: this is needed to communicate between the pinctrl driver and
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* the PM implementation in the machine. Possibly part of the PM
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* implementation should be moved down into the pinctrl driver and get
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* called as part of the generic suspend/resume path.
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*/
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#ifdef CONFIG_PINCTRL_AT91
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extern void at91_pinctrl_gpio_suspend(void);
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extern void at91_pinctrl_gpio_resume(void);
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#endif
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static struct {
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unsigned long uhp_udp_mask;
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int memctrl;
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} at91_pm_data;
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void __iomem *at91_ramc_base[2];
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static int at91_pm_valid_state(suspend_state_t state)
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{
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switch (state) {
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case PM_SUSPEND_ON:
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case PM_SUSPEND_STANDBY:
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case PM_SUSPEND_MEM:
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return 1;
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default:
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return 0;
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}
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}
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static suspend_state_t target_state;
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/*
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* Called after processes are frozen, but before we shutdown devices.
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*/
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static int at91_pm_begin(suspend_state_t state)
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{
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target_state = state;
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return 0;
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}
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/*
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* Verify that all the clocks are correct before entering
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* slow-clock mode.
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*/
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static int at91_pm_verify_clocks(void)
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{
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unsigned long scsr;
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int i;
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scsr = at91_pmc_read(AT91_PMC_SCSR);
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/* USB must not be using PLLB */
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if ((scsr & at91_pm_data.uhp_udp_mask) != 0) {
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pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
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return 0;
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}
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/* PCK0..PCK3 must be disabled, or configured to use clk32k */
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for (i = 0; i < 4; i++) {
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u32 css;
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if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
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continue;
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css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
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if (css != AT91_PMC_CSS_SLOW) {
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pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
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return 0;
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}
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}
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return 1;
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}
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/*
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* Call this from platform driver suspend() to see how deeply to suspend.
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* For example, some controllers (like OHCI) need one of the PLL clocks
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* in order to act as a wakeup source, and those are not available when
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* going into slow clock mode.
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*
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* REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
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* the very same problem (but not using at91 main_clk), and it'd be better
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* to add one generic API rather than lots of platform-specific ones.
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*/
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int at91_suspend_entering_slow_clock(void)
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{
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return (target_state == PM_SUSPEND_MEM);
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}
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EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
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static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0,
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void __iomem *ramc1, int memctrl);
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extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0,
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void __iomem *ramc1, int memctrl);
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extern u32 at91_pm_suspend_in_sram_sz;
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static void at91_pm_suspend(suspend_state_t state)
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{
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unsigned int pm_data = at91_pm_data.memctrl;
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pm_data |= (state == PM_SUSPEND_MEM) ?
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AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
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flush_cache_all();
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outer_disable();
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at91_suspend_sram_fn(at91_pmc_base, at91_ramc_base[0],
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at91_ramc_base[1], pm_data);
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outer_resume();
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}
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static int at91_pm_enter(suspend_state_t state)
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{
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#ifdef CONFIG_PINCTRL_AT91
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at91_pinctrl_gpio_suspend();
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#endif
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switch (state) {
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/*
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* Suspend-to-RAM is like STANDBY plus slow clock mode, so
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* drivers must suspend more deeply, the master clock switches
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* to the clk32k and turns off the main oscillator
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*/
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case PM_SUSPEND_MEM:
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/*
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* Ensure that clocks are in a valid state.
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*/
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if (!at91_pm_verify_clocks())
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goto error;
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at91_pm_suspend(state);
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break;
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/*
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* STANDBY mode has *all* drivers suspended; ignores irqs not
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* marked as 'wakeup' event sources; and reduces DRAM power.
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* But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
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* nothing fancy done with main or cpu clocks.
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*/
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case PM_SUSPEND_STANDBY:
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at91_pm_suspend(state);
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break;
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case PM_SUSPEND_ON:
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cpu_do_idle();
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break;
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default:
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pr_debug("AT91: PM - bogus suspend state %d\n", state);
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goto error;
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}
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error:
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target_state = PM_SUSPEND_ON;
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#ifdef CONFIG_PINCTRL_AT91
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at91_pinctrl_gpio_resume();
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#endif
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return 0;
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}
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/*
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* Called right prior to thawing processes.
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*/
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static void at91_pm_end(void)
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{
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target_state = PM_SUSPEND_ON;
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}
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static const struct platform_suspend_ops at91_pm_ops = {
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.valid = at91_pm_valid_state,
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.begin = at91_pm_begin,
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.enter = at91_pm_enter,
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.end = at91_pm_end,
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};
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static struct platform_device at91_cpuidle_device = {
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.name = "cpuidle-at91",
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};
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static void at91_pm_set_standby(void (*at91_standby)(void))
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{
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if (at91_standby)
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at91_cpuidle_device.dev.platform_data = at91_standby;
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}
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/*
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* The AT91RM9200 goes into self-refresh mode with this command, and will
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* terminate self-refresh automatically on the next SDRAM access.
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*
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* Self-refresh mode is exited as soon as a memory access is made, but we don't
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* know for sure when that happens. However, we need to restore the low-power
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* mode if it was enabled before going idle. Restoring low-power mode while
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* still in self-refresh is "not recommended", but seems to work.
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*/
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static void at91rm9200_standby(void)
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{
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u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR);
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asm volatile(
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"b 1f\n\t"
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".align 5\n\t"
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"1: mcr p15, 0, %0, c7, c10, 4\n\t"
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" str %0, [%1, %2]\n\t"
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" str %3, [%1, %4]\n\t"
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" mcr p15, 0, %0, c7, c0, 4\n\t"
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" str %5, [%1, %2]"
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:
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: "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_MC_SDRAMC_LPR),
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"r" (1), "r" (AT91_MC_SDRAMC_SRR),
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"r" (lpr));
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}
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/* We manage both DDRAM/SDRAM controllers, we need more than one value to
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* remember.
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*/
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static void at91_ddr_standby(void)
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{
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/* Those two values allow us to delay self-refresh activation
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* to the maximum. */
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u32 lpr0, lpr1 = 0;
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u32 saved_lpr0, saved_lpr1 = 0;
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if (at91_ramc_base[1]) {
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saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
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lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
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lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
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}
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saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
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lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
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lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
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/* self-refresh mode now */
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at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
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if (at91_ramc_base[1])
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at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
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cpu_do_idle();
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at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
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if (at91_ramc_base[1])
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at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
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}
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/* We manage both DDRAM/SDRAM controllers, we need more than one value to
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* remember.
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*/
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static void at91sam9_sdram_standby(void)
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{
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u32 lpr0, lpr1 = 0;
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u32 saved_lpr0, saved_lpr1 = 0;
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if (at91_ramc_base[1]) {
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saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
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lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
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lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
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}
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saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
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lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
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lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
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/* self-refresh mode now */
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at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
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if (at91_ramc_base[1])
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at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
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cpu_do_idle();
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at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
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if (at91_ramc_base[1])
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at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
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}
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static const struct of_device_id const ramc_ids[] __initconst = {
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{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
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{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
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{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
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{ .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
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{ /*sentinel*/ }
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};
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static __init void at91_dt_ramc(void)
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{
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struct device_node *np;
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const struct of_device_id *of_id;
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int idx = 0;
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const void *standby = NULL;
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for_each_matching_node_and_match(np, ramc_ids, &of_id) {
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at91_ramc_base[idx] = of_iomap(np, 0);
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if (!at91_ramc_base[idx])
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panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
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if (!standby)
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standby = of_id->data;
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idx++;
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}
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if (!idx)
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panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
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if (!standby) {
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pr_warn("ramc no standby function available\n");
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return;
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}
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at91_pm_set_standby(standby);
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}
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static void __init at91_pm_sram_init(void)
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{
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struct gen_pool *sram_pool;
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phys_addr_t sram_pbase;
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unsigned long sram_base;
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struct device_node *node;
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struct platform_device *pdev = NULL;
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for_each_compatible_node(node, NULL, "mmio-sram") {
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pdev = of_find_device_by_node(node);
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if (pdev) {
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of_node_put(node);
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break;
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}
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}
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if (!pdev) {
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pr_warn("%s: failed to find sram device!\n", __func__);
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return;
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}
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sram_pool = gen_pool_get(&pdev->dev, NULL);
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if (!sram_pool) {
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pr_warn("%s: sram pool unavailable!\n", __func__);
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return;
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}
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sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
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if (!sram_base) {
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pr_warn("%s: unable to alloc sram!\n", __func__);
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return;
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}
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sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
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at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
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at91_pm_suspend_in_sram_sz, false);
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if (!at91_suspend_sram_fn) {
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pr_warn("SRAM: Could not map\n");
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return;
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}
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/* Copy the pm suspend handler to SRAM */
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at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
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&at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
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}
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static void __init at91_pm_init(void)
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{
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at91_pm_sram_init();
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if (at91_cpuidle_device.dev.platform_data)
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platform_device_register(&at91_cpuidle_device);
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if (at91_suspend_sram_fn)
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suspend_set_ops(&at91_pm_ops);
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else
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pr_info("AT91: PM not supported, due to no SRAM allocated\n");
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}
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void __init at91rm9200_pm_init(void)
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{
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at91_dt_ramc();
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/*
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* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
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*/
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at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
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at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
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at91_pm_data.memctrl = AT91_MEMCTRL_MC;
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at91_pm_init();
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}
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void __init at91sam9260_pm_init(void)
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{
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at91_dt_ramc();
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at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
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at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
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return at91_pm_init();
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}
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void __init at91sam9g45_pm_init(void)
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{
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at91_dt_ramc();
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at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
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at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
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return at91_pm_init();
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}
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void __init at91sam9x5_pm_init(void)
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{
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at91_dt_ramc();
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at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
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at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
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return at91_pm_init();
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}
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