Mike Mason cde274c0c7 powerpc/eeh: PERR/SERR bit settings during EEH device recovery ... The following patch restores the PERR and SERR bits in the PCI command register during an EEH device recovery. We have found at least one case (an Agilent test card) where the PERR/SERR bits are set to 1 by firmware at boot time, but are not restored to 1 during EEH recovery. The patch fixes the Agilent card problem. It has been tested on several other EEH-enabled cards with no regressions. Signed-off-by: Mike Mason <mmlnx@us.ibm.com> Acked-by: Linas Vepstas <linasvepstas@gmail.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		2008-07-09 16:30:48 +10:00
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powerpc	powerpc/eeh: PERR/SERR bit settings during EEH device recovery	2008-07-09 16:30:48 +10:00
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