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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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76ae658465
This patch provides functions to lock & unlock access to the "core-other" register region of the CPC. Without performing appropriate locking it is possible for code using this region to be preempted or to race with code on another VPE within the same core, with one changing the core which the "core-other" region is acting upon at an inopportune time for the other. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
183 lines
5.8 KiB
C
183 lines
5.8 KiB
C
/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __MIPS_ASM_MIPS_CPC_H__
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#define __MIPS_ASM_MIPS_CPC_H__
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#include <linux/io.h>
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#include <linux/types.h>
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/* The base address of the CPC registers */
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extern void __iomem *mips_cpc_base;
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/**
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* mips_cpc_default_phys_base - retrieve the default physical base address of
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* the CPC
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*
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* Returns the default physical base address of the Cluster Power Controller
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* memory mapped registers. This is platform dependant & must therefore be
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* implemented per-platform.
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*/
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extern phys_t mips_cpc_default_phys_base(void);
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/**
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* mips_cpc_phys_base - retrieve the physical base address of the CPC
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*
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* This function returns the physical base address of the Cluster Power
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* Controller memory mapped registers, or 0 if no Cluster Power Controller
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* is present. It may be overriden by individual platforms which determine
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* this address in a different way.
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*/
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extern phys_t __weak mips_cpc_phys_base(void);
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/**
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* mips_cpc_probe - probe for a Cluster Power Controller
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*
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* Attempt to detect the presence of a Cluster Power Controller. Returns 0 if
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* a CPC is successfully detected, else -errno.
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*/
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#ifdef CONFIG_MIPS_CPC
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extern int mips_cpc_probe(void);
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#else
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static inline int mips_cpc_probe(void)
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{
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return -ENODEV;
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}
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#endif
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/**
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* mips_cpc_present - determine whether a Cluster Power Controller is present
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*
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* Returns true if a CPC is present in the system, else false.
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*/
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static inline bool mips_cpc_present(void)
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{
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#ifdef CONFIG_MIPS_CPC
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return mips_cpc_base != NULL;
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#else
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return false;
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#endif
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}
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/* Offsets from the CPC base address to various control blocks */
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#define MIPS_CPC_GCB_OFS 0x0000
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#define MIPS_CPC_CLCB_OFS 0x2000
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#define MIPS_CPC_COCB_OFS 0x4000
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/* Macros to ease the creation of register access functions */
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#define BUILD_CPC_R_(name, off) \
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static inline u32 *addr_cpc_##name(void) \
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{ \
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return (u32 *)(mips_cpc_base + (off)); \
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} \
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\
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static inline u32 read_cpc_##name(void) \
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{ \
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return __raw_readl(mips_cpc_base + (off)); \
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}
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#define BUILD_CPC__W(name, off) \
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static inline void write_cpc_##name(u32 value) \
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{ \
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__raw_writel(value, mips_cpc_base + (off)); \
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}
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#define BUILD_CPC_RW(name, off) \
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BUILD_CPC_R_(name, off) \
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BUILD_CPC__W(name, off)
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#define BUILD_CPC_Cx_R_(name, off) \
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BUILD_CPC_R_(cl_##name, MIPS_CPC_CLCB_OFS + (off)) \
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BUILD_CPC_R_(co_##name, MIPS_CPC_COCB_OFS + (off))
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#define BUILD_CPC_Cx__W(name, off) \
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BUILD_CPC__W(cl_##name, MIPS_CPC_CLCB_OFS + (off)) \
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BUILD_CPC__W(co_##name, MIPS_CPC_COCB_OFS + (off))
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#define BUILD_CPC_Cx_RW(name, off) \
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BUILD_CPC_Cx_R_(name, off) \
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BUILD_CPC_Cx__W(name, off)
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/* GCB register accessor functions */
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BUILD_CPC_RW(access, MIPS_CPC_GCB_OFS + 0x00)
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BUILD_CPC_RW(seqdel, MIPS_CPC_GCB_OFS + 0x08)
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BUILD_CPC_RW(rail, MIPS_CPC_GCB_OFS + 0x10)
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BUILD_CPC_RW(resetlen, MIPS_CPC_GCB_OFS + 0x18)
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BUILD_CPC_R_(revision, MIPS_CPC_GCB_OFS + 0x20)
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/* Core Local & Core Other accessor functions */
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BUILD_CPC_Cx_RW(cmd, 0x00)
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BUILD_CPC_Cx_RW(stat_conf, 0x08)
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BUILD_CPC_Cx_RW(other, 0x10)
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/* CPC_Cx_CMD register fields */
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#define CPC_Cx_CMD_SHF 0
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#define CPC_Cx_CMD_MSK (_ULCAST_(0xf) << 0)
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#define CPC_Cx_CMD_CLOCKOFF (_ULCAST_(0x1) << 0)
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#define CPC_Cx_CMD_PWRDOWN (_ULCAST_(0x2) << 0)
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#define CPC_Cx_CMD_PWRUP (_ULCAST_(0x3) << 0)
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#define CPC_Cx_CMD_RESET (_ULCAST_(0x4) << 0)
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/* CPC_Cx_STAT_CONF register fields */
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#define CPC_Cx_STAT_CONF_PWRUPE_SHF 23
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#define CPC_Cx_STAT_CONF_PWRUPE_MSK (_ULCAST_(0x1) << 23)
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#define CPC_Cx_STAT_CONF_SEQSTATE_SHF 19
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#define CPC_Cx_STAT_CONF_SEQSTATE_MSK (_ULCAST_(0xf) << 19)
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#define CPC_Cx_STAT_CONF_SEQSTATE_D0 (_ULCAST_(0x0) << 19)
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#define CPC_Cx_STAT_CONF_SEQSTATE_U0 (_ULCAST_(0x1) << 19)
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#define CPC_Cx_STAT_CONF_SEQSTATE_U1 (_ULCAST_(0x2) << 19)
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#define CPC_Cx_STAT_CONF_SEQSTATE_U2 (_ULCAST_(0x3) << 19)
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#define CPC_Cx_STAT_CONF_SEQSTATE_U3 (_ULCAST_(0x4) << 19)
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#define CPC_Cx_STAT_CONF_SEQSTATE_U4 (_ULCAST_(0x5) << 19)
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#define CPC_Cx_STAT_CONF_SEQSTATE_U5 (_ULCAST_(0x6) << 19)
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#define CPC_Cx_STAT_CONF_SEQSTATE_U6 (_ULCAST_(0x7) << 19)
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#define CPC_Cx_STAT_CONF_SEQSTATE_D1 (_ULCAST_(0x8) << 19)
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#define CPC_Cx_STAT_CONF_SEQSTATE_D3 (_ULCAST_(0x9) << 19)
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#define CPC_Cx_STAT_CONF_SEQSTATE_D2 (_ULCAST_(0xa) << 19)
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#define CPC_Cx_STAT_CONF_CLKGAT_IMPL_SHF 17
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#define CPC_Cx_STAT_CONF_CLKGAT_IMPL_MSK (_ULCAST_(0x1) << 17)
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#define CPC_Cx_STAT_CONF_PWRDN_IMPL_SHF 16
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#define CPC_Cx_STAT_CONF_PWRDN_IMPL_MSK (_ULCAST_(0x1) << 16)
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#define CPC_Cx_STAT_CONF_EJTAG_PROBE_SHF 15
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#define CPC_Cx_STAT_CONF_EJTAG_PROBE_MSK (_ULCAST_(0x1) << 15)
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/* CPC_Cx_OTHER register fields */
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#define CPC_Cx_OTHER_CORENUM_SHF 16
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#define CPC_Cx_OTHER_CORENUM_MSK (_ULCAST_(0xff) << 16)
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#ifdef CONFIG_MIPS_CPC
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/**
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* mips_cpc_lock_other - lock access to another core
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* core: the other core to be accessed
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*
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* Call before operating upon a core via the 'other' register region in
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* order to prevent the region being moved during access. Must be followed
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* by a call to mips_cpc_unlock_other.
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*/
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extern void mips_cpc_lock_other(unsigned int core);
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/**
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* mips_cpc_unlock_other - unlock access to another core
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*
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* Call after operating upon another core via the 'other' register region.
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* Must be called after mips_cpc_lock_other.
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*/
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extern void mips_cpc_unlock_other(void);
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#else /* !CONFIG_MIPS_CPC */
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static inline void mips_cpc_lock_other(unsigned int core) { }
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static inline void mips_cpc_unlock_other(void) { }
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#endif /* !CONFIG_MIPS_CPC */
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#endif /* __MIPS_ASM_MIPS_CPC_H__ */
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