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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c4a987db1b
Tips of Loongson's CPU hotplug: 1, To fully shutdown a core in Loongson 3, the target core should go to CKSEG1 and flush all L1 cache entries at first. Then, another core (usually Core 0) can safely disable the clock of the target core. So play_dead() call loongson3_play_dead() via CKSEG1 (both uncached and unmmaped). 2, The default clocksource of Loongson is MIPS. Since clock source is a global device, timekeeping need the CP0' Count registers of each core be synchronous. Thus, when a core is up, we use a SMP_ASK_C0COUNT IPI to ask Core-0's Count. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Hongliang Tao <taohl@lemote.com> Signed-off-by: Hua Yan <yanh@lemote.com> Tested-by: Alex Smith <alex.smith@imgtec.com> Reviewed-by: Alex Smith <alex.smith@imgtec.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/6639 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
45 lines
1.6 KiB
C
45 lines
1.6 KiB
C
#ifndef __ASM_MACH_LOONGSON_IRQ_H_
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#define __ASM_MACH_LOONGSON_IRQ_H_
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#include <boot_param.h>
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#ifdef CONFIG_CPU_LOONGSON3
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/* cpu core interrupt numbers */
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#define MIPS_CPU_IRQ_BASE 56
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#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */
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#define LOONGSON_HT1_IRQ (MIPS_CPU_IRQ_BASE + 3) /* HT1 */
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#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */
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#define LOONGSON_HT1_CFG_BASE loongson_sysconf.ht_control_base
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#define LOONGSON_HT1_INT_VECTOR_BASE (LOONGSON_HT1_CFG_BASE + 0x80)
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#define LOONGSON_HT1_INT_EN_BASE (LOONGSON_HT1_CFG_BASE + 0xa0)
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#define LOONGSON_HT1_INT_VECTOR(n) \
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LOONGSON3_REG32(LOONGSON_HT1_INT_VECTOR_BASE, 4 * (n))
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#define LOONGSON_HT1_INTN_EN(n) \
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LOONGSON3_REG32(LOONGSON_HT1_INT_EN_BASE, 4 * (n))
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#define LOONGSON_INT_ROUTER_OFFSET 0x1400
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#define LOONGSON_INT_ROUTER_INTEN \
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LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x24)
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#define LOONGSON_INT_ROUTER_INTENSET \
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LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x28)
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#define LOONGSON_INT_ROUTER_INTENCLR \
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LOONGSON3_REG32(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + 0x2c)
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#define LOONGSON_INT_ROUTER_ENTRY(n) \
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LOONGSON3_REG8(LOONGSON3_REG_BASE, LOONGSON_INT_ROUTER_OFFSET + n)
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#define LOONGSON_INT_ROUTER_LPC LOONGSON_INT_ROUTER_ENTRY(0x0a)
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#define LOONGSON_INT_ROUTER_HT1(n) LOONGSON_INT_ROUTER_ENTRY(n + 0x18)
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#define LOONGSON_INT_CORE0_INT0 0x11 /* route to int 0 of core 0 */
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#define LOONGSON_INT_CORE0_INT1 0x21 /* route to int 1 of core 0 */
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#endif
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extern void fixup_irqs(void);
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extern void loongson3_ipi_interrupt(struct pt_regs *regs);
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#include_next <irq.h>
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#endif /* __ASM_MACH_LOONGSON_IRQ_H_ */
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