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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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d198b514bd
Split the existing cm44xx.h file into cm1_44xx.h and cm2_44xx.h files so they match their underlying OMAP hardware modules. Add clockdomain offset information. Add header files for the MPU local PRCM, prcm_mpu44xx.h, and for the SCRM, scrm44xx.h. SCRM register offsets still need to be added; TI should do this. Move the "_MOD" macros out of the prcm-common.h header file, into the header file of the hardware module that they belong to. For example, OMAP4430_PRM_*_MOD macros have been moved into the prm44xx.h header. Adjust #includes of all files that used the old PRCM header file names to point to the new filenames. The autogeneration scripts have been updated accordingly. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Reviewed-by: Kevin Hilman <khilman@deeprootsystems.com> Tested-by: Kevin Hilman <khilman@deeprootsystems.com> Tested-by: Rajendra Nayak <rnayak@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
285 lines
8.7 KiB
C
285 lines
8.7 KiB
C
/*
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* OMAP4 Clock domains framework
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*
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* Copyright (C) 2009 Texas Instruments, Inc.
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* Copyright (C) 2009 Nokia Corporation
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*
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* Abhijit Pagare (abhijitpagare@ti.com)
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* Benoit Cousson (b-cousson@ti.com)
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*
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* This file is automatically generated from the OMAP hardware databases.
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* We respectfully ask that any modifications to this file be coordinated
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* with the public linux-omap@vger.kernel.org mailing list and the
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* authors above to ensure that the autogeneration scripts are kept
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* up-to-date with the file contents.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* To-Do List
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* -> Populate the Sleep/Wakeup dependencies for the domains
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <plat/clockdomain.h>
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#include "cm1_44xx.h"
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#include "cm2_44xx.h"
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#include "cm-regbits-44xx.h"
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#include "prm44xx.h"
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#include "prcm_mpu44xx.h"
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static struct clockdomain l4_cefuse_44xx_clkdm = {
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.name = "l4_cefuse_clkdm",
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.pwrdm = { .name = "cefuse_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_CEFUSE_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l4_cfg_44xx_clkdm = {
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.name = "l4_cfg_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_L4CFG_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain tesla_44xx_clkdm = {
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.name = "tesla_clkdm",
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.pwrdm = { .name = "tesla_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_TESLA_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_gfx_44xx_clkdm = {
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.name = "l3_gfx_clkdm",
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.pwrdm = { .name = "gfx_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_GFX_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain ivahd_44xx_clkdm = {
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.name = "ivahd_clkdm",
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.pwrdm = { .name = "ivahd_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_IVAHD_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l4_secure_44xx_clkdm = {
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.name = "l4_secure_clkdm",
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.pwrdm = { .name = "l4per_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_L4SEC_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l4_per_44xx_clkdm = {
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.name = "l4_per_clkdm",
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.pwrdm = { .name = "l4per_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_L4PER_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain abe_44xx_clkdm = {
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.name = "abe_clkdm",
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.pwrdm = { .name = "abe_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM1_ABE_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_instr_44xx_clkdm = {
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.name = "l3_instr_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_L3INSTR_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_init_44xx_clkdm = {
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.name = "l3_init_clkdm",
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.pwrdm = { .name = "l3init_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_L3INIT_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain mpuss_44xx_clkdm = {
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.name = "mpuss_clkdm",
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.pwrdm = { .name = "mpu_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_MPU_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain mpu0_44xx_clkdm = {
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.name = "mpu0_clkdm",
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.pwrdm = { .name = "cpu0_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_CPU0_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain mpu1_44xx_clkdm = {
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.name = "mpu1_clkdm",
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.pwrdm = { .name = "cpu1_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_CPU1_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_emif_44xx_clkdm = {
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.name = "l3_emif_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_MEMIF_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l4_ao_44xx_clkdm = {
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.name = "l4_ao_clkdm",
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.pwrdm = { .name = "always_on_core_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_ALWON_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain ducati_44xx_clkdm = {
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.name = "ducati_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_DUCATI_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_2_44xx_clkdm = {
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.name = "l3_2_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_L3_2_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_1_44xx_clkdm = {
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.name = "l3_1_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_L3_1_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_d2d_44xx_clkdm = {
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.name = "l3_d2d_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_D2D_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain iss_44xx_clkdm = {
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.name = "iss_clkdm",
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.pwrdm = { .name = "cam_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_CAM_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_dss_44xx_clkdm = {
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.name = "l3_dss_clkdm",
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.pwrdm = { .name = "dss_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_DSS_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP_SWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l4_wkup_44xx_clkdm = {
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.name = "l4_wkup_clkdm",
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.pwrdm = { .name = "wkup_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_WKUP_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain emu_sys_44xx_clkdm = {
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.name = "emu_sys_clkdm",
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.pwrdm = { .name = "emu_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_EMU_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain l3_dma_44xx_clkdm = {
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.name = "l3_dma_clkdm",
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.pwrdm = { .name = "core_pwrdm" },
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.clkstctrl_reg = OMAP4430_CM_SDMA_CLKSTCTRL,
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.clktrctrl_mask = OMAP4430_CLKTRCTRL_MASK,
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.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static struct clockdomain *clockdomains_omap44xx[] __initdata = {
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&l4_cefuse_44xx_clkdm,
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&l4_cfg_44xx_clkdm,
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&tesla_44xx_clkdm,
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&l3_gfx_44xx_clkdm,
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&ivahd_44xx_clkdm,
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&l4_secure_44xx_clkdm,
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&l4_per_44xx_clkdm,
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&abe_44xx_clkdm,
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&l3_instr_44xx_clkdm,
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&l3_init_44xx_clkdm,
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&mpuss_44xx_clkdm,
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&mpu0_44xx_clkdm,
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&mpu1_44xx_clkdm,
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&l3_emif_44xx_clkdm,
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&l4_ao_44xx_clkdm,
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&ducati_44xx_clkdm,
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&l3_2_44xx_clkdm,
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&l3_1_44xx_clkdm,
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&l3_d2d_44xx_clkdm,
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&iss_44xx_clkdm,
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&l3_dss_44xx_clkdm,
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&l4_wkup_44xx_clkdm,
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&emu_sys_44xx_clkdm,
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&l3_dma_44xx_clkdm,
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NULL,
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};
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void __init omap44xx_clockdomains_init(void)
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{
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clkdm_init(clockdomains_omap44xx, NULL);
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}
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