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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c3d5313001
Add support for cortex-a7-pmu present on ipq4019 SoCs. Signed-off-by: Thomas Pedersen <twp@codeaurora.org> Signed-off-by: Andy Gross <andy.gross@linaro.org>
274 lines
6.9 KiB
Plaintext
274 lines
6.9 KiB
Plaintext
/*
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* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/dts-v1/;
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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model = "Qualcomm Technologies, Inc. IPQ4019";
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compatible = "qcom,ipq4019";
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interrupt-parent = <&intc>;
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aliases {
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spi0 = &spi_0;
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i2c0 = &i2c_0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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enable-method = "qcom,kpss-acc-v1";
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qcom,acc = <&acc0>;
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qcom,saw = <&saw0>;
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reg = <0x0>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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operating-points = <
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/* kHz uV (fixed) */
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48000 1100000
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200000 1100000
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500000 1100000
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666000 1100000
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>;
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clock-latency = <256000>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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enable-method = "qcom,kpss-acc-v1";
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qcom,acc = <&acc1>;
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qcom,saw = <&saw1>;
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reg = <0x1>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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enable-method = "qcom,kpss-acc-v1";
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qcom,acc = <&acc2>;
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qcom,saw = <&saw2>;
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reg = <0x2>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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enable-method = "qcom,kpss-acc-v1";
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qcom,acc = <&acc3>;
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qcom,saw = <&saw3>;
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reg = <0x3>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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};
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};
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pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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clocks {
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sleep_clk: sleep_clk {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x0b000000 0x1000>,
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<0x0b002000 0x1000>;
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};
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gcc: clock-controller@1800000 {
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compatible = "qcom,gcc-ipq4019";
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#clock-cells = <1>;
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#reset-cells = <1>;
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reg = <0x1800000 0x60000>;
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};
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tlmm: pinctrl@0x01000000 {
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compatible = "qcom,ipq4019-pinctrl";
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reg = <0x01000000 0x300000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 208 0>;
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};
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blsp_dma: dma@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x07884000 0x23000>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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status = "disabled";
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};
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spi_0: spi@78b5000 {
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compatible = "qcom,spi-qup-v2.2.1";
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reg = <0x78b5000 0x600>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c_0: i2c@78b7000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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reg = <0x78b7000 0x6000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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cryptobam: dma@8e04000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x08e04000 0x20000>;
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interrupts = <GIC_SPI 207 0>;
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clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <1>;
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qcom,controlled-remotely;
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status = "disabled";
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};
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crypto@8e3a000 {
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compatible = "qcom,crypto-v5.1";
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reg = <0x08e3a000 0x6000>;
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clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
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<&gcc GCC_CRYPTO_AXI_CLK>,
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<&gcc GCC_CRYPTO_CLK>;
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clock-names = "iface", "bus", "core";
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dmas = <&cryptobam 2>, <&cryptobam 3>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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acc0: clock-controller@b088000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
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};
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acc1: clock-controller@b098000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
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};
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acc2: clock-controller@b0a8000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
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};
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acc3: clock-controller@b0b8000 {
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compatible = "qcom,kpss-acc-v1";
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reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
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};
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saw0: regulator@b089000 {
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compatible = "qcom,saw2";
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reg = <0x02089000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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};
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saw1: regulator@b099000 {
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compatible = "qcom,saw2";
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reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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};
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saw2: regulator@b0a9000 {
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compatible = "qcom,saw2";
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reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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};
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saw3: regulator@b0b9000 {
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compatible = "qcom,saw2";
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reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
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regulator;
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};
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serial@78af000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78af000 0x200>;
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interrupts = <0 107 0>;
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status = "disabled";
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clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp_dma 1>, <&blsp_dma 0>;
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dma-names = "rx", "tx";
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};
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serial@78b0000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x78b0000 0x200>;
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interrupts = <0 108 0>;
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status = "disabled";
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clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp_dma 3>, <&blsp_dma 2>;
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dma-names = "rx", "tx";
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};
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watchdog@b017000 {
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compatible = "qcom,kpss-standalone";
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reg = <0xb017000 0x40>;
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clocks = <&sleep_clk>;
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timeout-sec = <10>;
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status = "disabled";
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};
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restart@4ab000 {
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compatible = "qcom,pshold";
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reg = <0x4ab000 0x4>;
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};
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};
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};
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