mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
674f368a95
The CRYPTO_TFM_RES_BAD_KEY_LEN flag was apparently meant as a way to make the ->setkey() functions provide more information about errors. However, no one actually checks for this flag, which makes it pointless. Also, many algorithms fail to set this flag when given a bad length key. Reviewing just the generic implementations, this is the case for aes-fixed-time, cbcmac, echainiv, nhpoly1305, pcrypt, rfc3686, rfc4309, rfc7539, rfc7539esp, salsa20, seqiv, and xcbc. But there are probably many more in arch/*/crypto/ and drivers/crypto/. Some algorithms can even set this flag when the key is the correct length. For example, authenc and authencesn set it when the key payload is malformed in any way (not just a bad length), the atmel-sha and ccree drivers can set it if a memory allocation fails, and the chelsio driver sets it for bad auth tag lengths, not just bad key lengths. So even if someone actually wanted to start checking this flag (which seems unlikely, since it's been unused for a long time), there would be a lot of work needed to get it working correctly. But it would probably be much better to go back to the drawing board and just define different return values, like -EINVAL if the key is invalid for the algorithm vs. -EKEYREJECTED if the key was rejected by a policy like "no weak keys". That would be much simpler, less error-prone, and easier to test. So just remove this flag. Signed-off-by: Eric Biggers <ebiggers@google.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
556 lines
14 KiB
C
556 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
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*/
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <crypto/internal/hash.h>
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#include "common.h"
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#include "core.h"
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#include "sha.h"
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/* crypto hw padding constant for first operation */
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#define SHA_PADDING 64
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#define SHA_PADDING_MASK (SHA_PADDING - 1)
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static LIST_HEAD(ahash_algs);
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static const u32 std_iv_sha1[SHA256_DIGEST_SIZE / sizeof(u32)] = {
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SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4, 0, 0, 0
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};
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static const u32 std_iv_sha256[SHA256_DIGEST_SIZE / sizeof(u32)] = {
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SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3,
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SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7
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};
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static void qce_ahash_done(void *data)
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{
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struct crypto_async_request *async_req = data;
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struct ahash_request *req = ahash_request_cast(async_req);
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struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
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struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
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struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm);
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struct qce_device *qce = tmpl->qce;
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struct qce_result_dump *result = qce->dma.result_buf;
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unsigned int digestsize = crypto_ahash_digestsize(ahash);
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int error;
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u32 status;
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error = qce_dma_terminate_all(&qce->dma);
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if (error)
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dev_dbg(qce->dev, "ahash dma termination error (%d)\n", error);
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dma_unmap_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
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dma_unmap_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
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memcpy(rctx->digest, result->auth_iv, digestsize);
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if (req->result)
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memcpy(req->result, result->auth_iv, digestsize);
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rctx->byte_count[0] = cpu_to_be32(result->auth_byte_count[0]);
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rctx->byte_count[1] = cpu_to_be32(result->auth_byte_count[1]);
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error = qce_check_status(qce, &status);
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if (error < 0)
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dev_dbg(qce->dev, "ahash operation error (%x)\n", status);
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req->src = rctx->src_orig;
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req->nbytes = rctx->nbytes_orig;
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rctx->last_blk = false;
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rctx->first_blk = false;
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qce->async_req_done(tmpl->qce, error);
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}
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static int qce_ahash_async_req_handle(struct crypto_async_request *async_req)
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{
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struct ahash_request *req = ahash_request_cast(async_req);
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struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
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struct qce_sha_ctx *ctx = crypto_tfm_ctx(async_req->tfm);
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struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm);
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struct qce_device *qce = tmpl->qce;
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unsigned long flags = rctx->flags;
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int ret;
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if (IS_SHA_HMAC(flags)) {
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rctx->authkey = ctx->authkey;
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rctx->authklen = QCE_SHA_HMAC_KEY_SIZE;
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} else if (IS_CMAC(flags)) {
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rctx->authkey = ctx->authkey;
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rctx->authklen = AES_KEYSIZE_128;
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}
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rctx->src_nents = sg_nents_for_len(req->src, req->nbytes);
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if (rctx->src_nents < 0) {
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dev_err(qce->dev, "Invalid numbers of src SG.\n");
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return rctx->src_nents;
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}
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ret = dma_map_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
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if (ret < 0)
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return ret;
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sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ);
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ret = dma_map_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
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if (ret < 0)
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goto error_unmap_src;
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ret = qce_dma_prep_sgs(&qce->dma, req->src, rctx->src_nents,
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&rctx->result_sg, 1, qce_ahash_done, async_req);
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if (ret)
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goto error_unmap_dst;
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qce_dma_issue_pending(&qce->dma);
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ret = qce_start(async_req, tmpl->crypto_alg_type, 0, 0);
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if (ret)
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goto error_terminate;
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return 0;
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error_terminate:
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qce_dma_terminate_all(&qce->dma);
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error_unmap_dst:
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dma_unmap_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
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error_unmap_src:
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dma_unmap_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
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return ret;
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}
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static int qce_ahash_init(struct ahash_request *req)
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{
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struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
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struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
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const u32 *std_iv = tmpl->std_iv;
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memset(rctx, 0, sizeof(*rctx));
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rctx->first_blk = true;
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rctx->last_blk = false;
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rctx->flags = tmpl->alg_flags;
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memcpy(rctx->digest, std_iv, sizeof(rctx->digest));
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return 0;
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}
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static int qce_ahash_export(struct ahash_request *req, void *out)
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{
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struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
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struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
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unsigned long flags = rctx->flags;
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unsigned int digestsize = crypto_ahash_digestsize(ahash);
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unsigned int blocksize =
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crypto_tfm_alg_blocksize(crypto_ahash_tfm(ahash));
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if (IS_SHA1(flags) || IS_SHA1_HMAC(flags)) {
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struct sha1_state *out_state = out;
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out_state->count = rctx->count;
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qce_cpu_to_be32p_array((__be32 *)out_state->state,
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rctx->digest, digestsize);
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memcpy(out_state->buffer, rctx->buf, blocksize);
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} else if (IS_SHA256(flags) || IS_SHA256_HMAC(flags)) {
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struct sha256_state *out_state = out;
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out_state->count = rctx->count;
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qce_cpu_to_be32p_array((__be32 *)out_state->state,
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rctx->digest, digestsize);
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memcpy(out_state->buf, rctx->buf, blocksize);
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} else {
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return -EINVAL;
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}
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return 0;
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}
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static int qce_import_common(struct ahash_request *req, u64 in_count,
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const u32 *state, const u8 *buffer, bool hmac)
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{
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struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
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struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
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unsigned int digestsize = crypto_ahash_digestsize(ahash);
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unsigned int blocksize;
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u64 count = in_count;
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blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(ahash));
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rctx->count = in_count;
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memcpy(rctx->buf, buffer, blocksize);
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if (in_count <= blocksize) {
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rctx->first_blk = 1;
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} else {
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rctx->first_blk = 0;
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/*
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* For HMAC, there is a hardware padding done when first block
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* is set. Therefore the byte_count must be incremened by 64
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* after the first block operation.
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*/
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if (hmac)
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count += SHA_PADDING;
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}
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rctx->byte_count[0] = (__force __be32)(count & ~SHA_PADDING_MASK);
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rctx->byte_count[1] = (__force __be32)(count >> 32);
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qce_cpu_to_be32p_array((__be32 *)rctx->digest, (const u8 *)state,
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digestsize);
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rctx->buflen = (unsigned int)(in_count & (blocksize - 1));
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return 0;
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}
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static int qce_ahash_import(struct ahash_request *req, const void *in)
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{
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struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
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unsigned long flags = rctx->flags;
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bool hmac = IS_SHA_HMAC(flags);
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int ret = -EINVAL;
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if (IS_SHA1(flags) || IS_SHA1_HMAC(flags)) {
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const struct sha1_state *state = in;
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ret = qce_import_common(req, state->count, state->state,
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state->buffer, hmac);
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} else if (IS_SHA256(flags) || IS_SHA256_HMAC(flags)) {
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const struct sha256_state *state = in;
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ret = qce_import_common(req, state->count, state->state,
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state->buf, hmac);
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}
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return ret;
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}
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static int qce_ahash_update(struct ahash_request *req)
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{
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struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
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struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
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struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
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struct qce_device *qce = tmpl->qce;
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struct scatterlist *sg_last, *sg;
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unsigned int total, len;
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unsigned int hash_later;
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unsigned int nbytes;
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unsigned int blocksize;
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blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
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rctx->count += req->nbytes;
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/* check for buffer from previous updates and append it */
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total = req->nbytes + rctx->buflen;
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if (total <= blocksize) {
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scatterwalk_map_and_copy(rctx->buf + rctx->buflen, req->src,
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0, req->nbytes, 0);
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rctx->buflen += req->nbytes;
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return 0;
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}
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/* save the original req structure fields */
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rctx->src_orig = req->src;
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rctx->nbytes_orig = req->nbytes;
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/*
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* if we have data from previous update copy them on buffer. The old
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* data will be combined with current request bytes.
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*/
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if (rctx->buflen)
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memcpy(rctx->tmpbuf, rctx->buf, rctx->buflen);
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/* calculate how many bytes will be hashed later */
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hash_later = total % blocksize;
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if (hash_later) {
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unsigned int src_offset = req->nbytes - hash_later;
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scatterwalk_map_and_copy(rctx->buf, req->src, src_offset,
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hash_later, 0);
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}
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/* here nbytes is multiple of blocksize */
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nbytes = total - hash_later;
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len = rctx->buflen;
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sg = sg_last = req->src;
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while (len < nbytes && sg) {
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if (len + sg_dma_len(sg) > nbytes)
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break;
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len += sg_dma_len(sg);
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sg_last = sg;
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sg = sg_next(sg);
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}
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if (!sg_last)
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return -EINVAL;
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sg_mark_end(sg_last);
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if (rctx->buflen) {
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sg_init_table(rctx->sg, 2);
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sg_set_buf(rctx->sg, rctx->tmpbuf, rctx->buflen);
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sg_chain(rctx->sg, 2, req->src);
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req->src = rctx->sg;
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}
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req->nbytes = nbytes;
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rctx->buflen = hash_later;
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return qce->async_req_enqueue(tmpl->qce, &req->base);
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}
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static int qce_ahash_final(struct ahash_request *req)
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{
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struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
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struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
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struct qce_device *qce = tmpl->qce;
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if (!rctx->buflen)
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return 0;
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rctx->last_blk = true;
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rctx->src_orig = req->src;
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rctx->nbytes_orig = req->nbytes;
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memcpy(rctx->tmpbuf, rctx->buf, rctx->buflen);
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sg_init_one(rctx->sg, rctx->tmpbuf, rctx->buflen);
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req->src = rctx->sg;
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req->nbytes = rctx->buflen;
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return qce->async_req_enqueue(tmpl->qce, &req->base);
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}
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static int qce_ahash_digest(struct ahash_request *req)
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{
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struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
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struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
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struct qce_device *qce = tmpl->qce;
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int ret;
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ret = qce_ahash_init(req);
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if (ret)
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return ret;
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rctx->src_orig = req->src;
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rctx->nbytes_orig = req->nbytes;
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rctx->first_blk = true;
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rctx->last_blk = true;
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return qce->async_req_enqueue(tmpl->qce, &req->base);
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}
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static int qce_ahash_hmac_setkey(struct crypto_ahash *tfm, const u8 *key,
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unsigned int keylen)
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{
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unsigned int digestsize = crypto_ahash_digestsize(tfm);
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struct qce_sha_ctx *ctx = crypto_tfm_ctx(&tfm->base);
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struct crypto_wait wait;
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struct ahash_request *req;
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struct scatterlist sg;
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unsigned int blocksize;
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struct crypto_ahash *ahash_tfm;
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u8 *buf;
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int ret;
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const char *alg_name;
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blocksize = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
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memset(ctx->authkey, 0, sizeof(ctx->authkey));
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if (keylen <= blocksize) {
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memcpy(ctx->authkey, key, keylen);
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return 0;
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}
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if (digestsize == SHA1_DIGEST_SIZE)
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alg_name = "sha1-qce";
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else if (digestsize == SHA256_DIGEST_SIZE)
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alg_name = "sha256-qce";
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else
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return -EINVAL;
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ahash_tfm = crypto_alloc_ahash(alg_name, 0, 0);
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if (IS_ERR(ahash_tfm))
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return PTR_ERR(ahash_tfm);
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req = ahash_request_alloc(ahash_tfm, GFP_KERNEL);
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if (!req) {
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ret = -ENOMEM;
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goto err_free_ahash;
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}
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crypto_init_wait(&wait);
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ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
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crypto_req_done, &wait);
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crypto_ahash_clear_flags(ahash_tfm, ~0);
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buf = kzalloc(keylen + QCE_MAX_ALIGN_SIZE, GFP_KERNEL);
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if (!buf) {
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ret = -ENOMEM;
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goto err_free_req;
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}
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memcpy(buf, key, keylen);
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sg_init_one(&sg, buf, keylen);
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ahash_request_set_crypt(req, &sg, ctx->authkey, keylen);
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ret = crypto_wait_req(crypto_ahash_digest(req), &wait);
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kfree(buf);
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err_free_req:
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ahash_request_free(req);
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err_free_ahash:
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crypto_free_ahash(ahash_tfm);
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return ret;
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}
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static int qce_ahash_cra_init(struct crypto_tfm *tfm)
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{
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struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
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struct qce_sha_ctx *ctx = crypto_tfm_ctx(tfm);
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crypto_ahash_set_reqsize(ahash, sizeof(struct qce_sha_reqctx));
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memset(ctx, 0, sizeof(*ctx));
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return 0;
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}
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struct qce_ahash_def {
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unsigned long flags;
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const char *name;
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const char *drv_name;
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unsigned int digestsize;
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unsigned int blocksize;
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unsigned int statesize;
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const u32 *std_iv;
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};
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static const struct qce_ahash_def ahash_def[] = {
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{
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.flags = QCE_HASH_SHA1,
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.name = "sha1",
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.drv_name = "sha1-qce",
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.digestsize = SHA1_DIGEST_SIZE,
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.blocksize = SHA1_BLOCK_SIZE,
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.statesize = sizeof(struct sha1_state),
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.std_iv = std_iv_sha1,
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},
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{
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.flags = QCE_HASH_SHA256,
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.name = "sha256",
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.drv_name = "sha256-qce",
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.digestsize = SHA256_DIGEST_SIZE,
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.blocksize = SHA256_BLOCK_SIZE,
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.statesize = sizeof(struct sha256_state),
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.std_iv = std_iv_sha256,
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},
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{
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.flags = QCE_HASH_SHA1_HMAC,
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.name = "hmac(sha1)",
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.drv_name = "hmac-sha1-qce",
|
|
.digestsize = SHA1_DIGEST_SIZE,
|
|
.blocksize = SHA1_BLOCK_SIZE,
|
|
.statesize = sizeof(struct sha1_state),
|
|
.std_iv = std_iv_sha1,
|
|
},
|
|
{
|
|
.flags = QCE_HASH_SHA256_HMAC,
|
|
.name = "hmac(sha256)",
|
|
.drv_name = "hmac-sha256-qce",
|
|
.digestsize = SHA256_DIGEST_SIZE,
|
|
.blocksize = SHA256_BLOCK_SIZE,
|
|
.statesize = sizeof(struct sha256_state),
|
|
.std_iv = std_iv_sha256,
|
|
},
|
|
};
|
|
|
|
static int qce_ahash_register_one(const struct qce_ahash_def *def,
|
|
struct qce_device *qce)
|
|
{
|
|
struct qce_alg_template *tmpl;
|
|
struct ahash_alg *alg;
|
|
struct crypto_alg *base;
|
|
int ret;
|
|
|
|
tmpl = kzalloc(sizeof(*tmpl), GFP_KERNEL);
|
|
if (!tmpl)
|
|
return -ENOMEM;
|
|
|
|
tmpl->std_iv = def->std_iv;
|
|
|
|
alg = &tmpl->alg.ahash;
|
|
alg->init = qce_ahash_init;
|
|
alg->update = qce_ahash_update;
|
|
alg->final = qce_ahash_final;
|
|
alg->digest = qce_ahash_digest;
|
|
alg->export = qce_ahash_export;
|
|
alg->import = qce_ahash_import;
|
|
if (IS_SHA_HMAC(def->flags))
|
|
alg->setkey = qce_ahash_hmac_setkey;
|
|
alg->halg.digestsize = def->digestsize;
|
|
alg->halg.statesize = def->statesize;
|
|
|
|
base = &alg->halg.base;
|
|
base->cra_blocksize = def->blocksize;
|
|
base->cra_priority = 300;
|
|
base->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY;
|
|
base->cra_ctxsize = sizeof(struct qce_sha_ctx);
|
|
base->cra_alignmask = 0;
|
|
base->cra_module = THIS_MODULE;
|
|
base->cra_init = qce_ahash_cra_init;
|
|
|
|
snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "%s", def->name);
|
|
snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
|
|
def->drv_name);
|
|
|
|
INIT_LIST_HEAD(&tmpl->entry);
|
|
tmpl->crypto_alg_type = CRYPTO_ALG_TYPE_AHASH;
|
|
tmpl->alg_flags = def->flags;
|
|
tmpl->qce = qce;
|
|
|
|
ret = crypto_register_ahash(alg);
|
|
if (ret) {
|
|
kfree(tmpl);
|
|
dev_err(qce->dev, "%s registration failed\n", base->cra_name);
|
|
return ret;
|
|
}
|
|
|
|
list_add_tail(&tmpl->entry, &ahash_algs);
|
|
dev_dbg(qce->dev, "%s is registered\n", base->cra_name);
|
|
return 0;
|
|
}
|
|
|
|
static void qce_ahash_unregister(struct qce_device *qce)
|
|
{
|
|
struct qce_alg_template *tmpl, *n;
|
|
|
|
list_for_each_entry_safe(tmpl, n, &ahash_algs, entry) {
|
|
crypto_unregister_ahash(&tmpl->alg.ahash);
|
|
list_del(&tmpl->entry);
|
|
kfree(tmpl);
|
|
}
|
|
}
|
|
|
|
static int qce_ahash_register(struct qce_device *qce)
|
|
{
|
|
int ret, i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(ahash_def); i++) {
|
|
ret = qce_ahash_register_one(&ahash_def[i], qce);
|
|
if (ret)
|
|
goto err;
|
|
}
|
|
|
|
return 0;
|
|
err:
|
|
qce_ahash_unregister(qce);
|
|
return ret;
|
|
}
|
|
|
|
const struct qce_algo_ops ahash_ops = {
|
|
.type = CRYPTO_ALG_TYPE_AHASH,
|
|
.register_algs = qce_ahash_register,
|
|
.unregister_algs = qce_ahash_unregister,
|
|
.async_req_handle = qce_ahash_async_req_handle,
|
|
};
|