mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 07:45:06 +07:00
80815004a4
The 2x outputs of the 2 video PLL clocks are directly used by the
HDMI controller block.
Export them so they can be referenced in the device tree.
Fixes: c6e6c96d8f ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
192 lines
5.4 KiB
C
192 lines
5.4 KiB
C
/*
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* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_
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#define _DT_BINDINGS_CLK_SUN6I_A31_H_
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#define CLK_PLL_VIDEO0_2X 7
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#define CLK_PLL_PERIPH 10
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#define CLK_PLL_VIDEO1_2X 13
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#define CLK_CPU 18
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#define CLK_AHB1_MIPIDSI 23
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#define CLK_AHB1_SS 24
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#define CLK_AHB1_DMA 25
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#define CLK_AHB1_MMC0 26
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#define CLK_AHB1_MMC1 27
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#define CLK_AHB1_MMC2 28
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#define CLK_AHB1_MMC3 29
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#define CLK_AHB1_NAND1 30
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#define CLK_AHB1_NAND0 31
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#define CLK_AHB1_SDRAM 32
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#define CLK_AHB1_EMAC 33
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#define CLK_AHB1_TS 34
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#define CLK_AHB1_HSTIMER 35
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#define CLK_AHB1_SPI0 36
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#define CLK_AHB1_SPI1 37
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#define CLK_AHB1_SPI2 38
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#define CLK_AHB1_SPI3 39
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#define CLK_AHB1_OTG 40
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#define CLK_AHB1_EHCI0 41
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#define CLK_AHB1_EHCI1 42
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#define CLK_AHB1_OHCI0 43
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#define CLK_AHB1_OHCI1 44
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#define CLK_AHB1_OHCI2 45
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#define CLK_AHB1_VE 46
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#define CLK_AHB1_LCD0 47
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#define CLK_AHB1_LCD1 48
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#define CLK_AHB1_CSI 49
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#define CLK_AHB1_HDMI 50
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#define CLK_AHB1_BE0 51
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#define CLK_AHB1_BE1 52
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#define CLK_AHB1_FE0 53
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#define CLK_AHB1_FE1 54
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#define CLK_AHB1_MP 55
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#define CLK_AHB1_GPU 56
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#define CLK_AHB1_DEU0 57
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#define CLK_AHB1_DEU1 58
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#define CLK_AHB1_DRC0 59
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#define CLK_AHB1_DRC1 60
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#define CLK_APB1_CODEC 61
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#define CLK_APB1_SPDIF 62
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#define CLK_APB1_DIGITAL_MIC 63
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#define CLK_APB1_PIO 64
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#define CLK_APB1_DAUDIO0 65
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#define CLK_APB1_DAUDIO1 66
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#define CLK_APB2_I2C0 67
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#define CLK_APB2_I2C1 68
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#define CLK_APB2_I2C2 69
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#define CLK_APB2_I2C3 70
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#define CLK_APB2_UART0 71
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#define CLK_APB2_UART1 72
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#define CLK_APB2_UART2 73
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#define CLK_APB2_UART3 74
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#define CLK_APB2_UART4 75
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#define CLK_APB2_UART5 76
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#define CLK_NAND0 77
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#define CLK_NAND1 78
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#define CLK_MMC0 79
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#define CLK_MMC0_SAMPLE 80
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#define CLK_MMC0_OUTPUT 81
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#define CLK_MMC1 82
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#define CLK_MMC1_SAMPLE 83
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#define CLK_MMC1_OUTPUT 84
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#define CLK_MMC2 85
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#define CLK_MMC2_SAMPLE 86
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#define CLK_MMC2_OUTPUT 87
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#define CLK_MMC3 88
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#define CLK_MMC3_SAMPLE 89
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#define CLK_MMC3_OUTPUT 90
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#define CLK_TS 91
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#define CLK_SS 92
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#define CLK_SPI0 93
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#define CLK_SPI1 94
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#define CLK_SPI2 95
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#define CLK_SPI3 96
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#define CLK_DAUDIO0 97
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#define CLK_DAUDIO1 98
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#define CLK_SPDIF 99
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#define CLK_USB_PHY0 100
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#define CLK_USB_PHY1 101
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#define CLK_USB_PHY2 102
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#define CLK_USB_OHCI0 103
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#define CLK_USB_OHCI1 104
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#define CLK_USB_OHCI2 105
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#define CLK_DRAM_VE 110
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#define CLK_DRAM_CSI_ISP 111
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#define CLK_DRAM_TS 112
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#define CLK_DRAM_DRC0 113
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#define CLK_DRAM_DRC1 114
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#define CLK_DRAM_DEU0 115
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#define CLK_DRAM_DEU1 116
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#define CLK_DRAM_FE0 117
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#define CLK_DRAM_FE1 118
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#define CLK_DRAM_BE0 119
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#define CLK_DRAM_BE1 120
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#define CLK_DRAM_MP 121
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#define CLK_BE0 122
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#define CLK_BE1 123
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#define CLK_FE0 124
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#define CLK_FE1 125
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#define CLK_MP 126
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#define CLK_LCD0_CH0 127
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#define CLK_LCD1_CH0 128
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#define CLK_LCD0_CH1 129
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#define CLK_LCD1_CH1 130
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#define CLK_CSI0_SCLK 131
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#define CLK_CSI0_MCLK 132
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#define CLK_CSI1_MCLK 133
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#define CLK_VE 134
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#define CLK_CODEC 135
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#define CLK_AVS 136
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#define CLK_DIGITAL_MIC 137
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#define CLK_HDMI 138
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#define CLK_HDMI_DDC 139
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#define CLK_PS 140
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#define CLK_MIPI_DSI 143
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#define CLK_MIPI_DSI_DPHY 144
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#define CLK_MIPI_CSI_DPHY 145
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#define CLK_IEP_DRC0 146
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#define CLK_IEP_DRC1 147
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#define CLK_IEP_DEU0 148
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#define CLK_IEP_DEU1 149
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#define CLK_GPU_CORE 150
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#define CLK_GPU_MEMORY 151
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#define CLK_GPU_HYD 152
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#define CLK_ATS 153
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#define CLK_TRACE 154
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#define CLK_OUT_A 155
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#define CLK_OUT_B 156
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#define CLK_OUT_C 157
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#endif /* _DT_BINDINGS_CLK_SUN6I_A31_H_ */
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