mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 08:47:24 +07:00
f8433f9e10
The Page Table Array is a new first level structure above the MTLB availabale on GPUs with the security feature. Use the PTa to set up the MMU when the security related states are handled by the kernel driver. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
349 lines
9.4 KiB
C
349 lines
9.4 KiB
C
/*
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* Copyright (C) 2016 Etnaviv Project
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/platform_device.h>
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#include <linux/sizes.h>
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#include <linux/slab.h>
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#include <linux/dma-mapping.h>
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#include <linux/bitops.h>
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#include "etnaviv_cmdbuf.h"
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#include "etnaviv_gpu.h"
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#include "etnaviv_mmu.h"
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#include "etnaviv_iommu.h"
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#include "state.xml.h"
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#include "state_hi.xml.h"
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#define MMUv2_PTE_PRESENT BIT(0)
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#define MMUv2_PTE_EXCEPTION BIT(1)
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#define MMUv2_PTE_WRITEABLE BIT(2)
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#define MMUv2_MTLB_MASK 0xffc00000
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#define MMUv2_MTLB_SHIFT 22
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#define MMUv2_STLB_MASK 0x003ff000
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#define MMUv2_STLB_SHIFT 12
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#define MMUv2_MAX_STLB_ENTRIES 1024
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struct etnaviv_iommuv2_domain {
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struct etnaviv_iommu_domain base;
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/* P(age) T(able) A(rray) */
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u64 *pta_cpu;
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dma_addr_t pta_dma;
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/* M(aster) TLB aka first level pagetable */
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u32 *mtlb_cpu;
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dma_addr_t mtlb_dma;
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/* S(lave) TLB aka second level pagetable */
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u32 *stlb_cpu[1024];
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dma_addr_t stlb_dma[1024];
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};
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static struct etnaviv_iommuv2_domain *
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to_etnaviv_domain(struct etnaviv_iommu_domain *domain)
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{
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return container_of(domain, struct etnaviv_iommuv2_domain, base);
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}
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static int etnaviv_iommuv2_map(struct etnaviv_iommu_domain *domain,
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unsigned long iova, phys_addr_t paddr,
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size_t size, int prot)
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{
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struct etnaviv_iommuv2_domain *etnaviv_domain =
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to_etnaviv_domain(domain);
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int mtlb_entry, stlb_entry;
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u32 entry = (u32)paddr | MMUv2_PTE_PRESENT;
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if (size != SZ_4K)
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return -EINVAL;
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if (prot & ETNAVIV_PROT_WRITE)
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entry |= MMUv2_PTE_WRITEABLE;
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mtlb_entry = (iova & MMUv2_MTLB_MASK) >> MMUv2_MTLB_SHIFT;
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stlb_entry = (iova & MMUv2_STLB_MASK) >> MMUv2_STLB_SHIFT;
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etnaviv_domain->stlb_cpu[mtlb_entry][stlb_entry] = entry;
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return 0;
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}
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static size_t etnaviv_iommuv2_unmap(struct etnaviv_iommu_domain *domain,
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unsigned long iova, size_t size)
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{
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struct etnaviv_iommuv2_domain *etnaviv_domain =
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to_etnaviv_domain(domain);
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int mtlb_entry, stlb_entry;
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if (size != SZ_4K)
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return -EINVAL;
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mtlb_entry = (iova & MMUv2_MTLB_MASK) >> MMUv2_MTLB_SHIFT;
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stlb_entry = (iova & MMUv2_STLB_MASK) >> MMUv2_STLB_SHIFT;
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etnaviv_domain->stlb_cpu[mtlb_entry][stlb_entry] = MMUv2_PTE_EXCEPTION;
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return SZ_4K;
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}
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static int etnaviv_iommuv2_init(struct etnaviv_iommuv2_domain *etnaviv_domain)
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{
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u32 *p;
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int ret, i, j;
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/* allocate scratch page */
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etnaviv_domain->base.bad_page_cpu = dma_alloc_coherent(
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etnaviv_domain->base.dev,
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SZ_4K,
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&etnaviv_domain->base.bad_page_dma,
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GFP_KERNEL);
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if (!etnaviv_domain->base.bad_page_cpu) {
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ret = -ENOMEM;
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goto fail_mem;
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}
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p = etnaviv_domain->base.bad_page_cpu;
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for (i = 0; i < SZ_4K / 4; i++)
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*p++ = 0xdead55aa;
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etnaviv_domain->pta_cpu = dma_alloc_coherent(etnaviv_domain->base.dev,
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SZ_4K,
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&etnaviv_domain->pta_dma,
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GFP_KERNEL);
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if (!etnaviv_domain->pta_cpu) {
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ret = -ENOMEM;
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goto fail_mem;
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}
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etnaviv_domain->mtlb_cpu = dma_alloc_coherent(etnaviv_domain->base.dev,
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SZ_4K,
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&etnaviv_domain->mtlb_dma,
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GFP_KERNEL);
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if (!etnaviv_domain->mtlb_cpu) {
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ret = -ENOMEM;
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goto fail_mem;
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}
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/* pre-populate STLB pages (may want to switch to on-demand later) */
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for (i = 0; i < MMUv2_MAX_STLB_ENTRIES; i++) {
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etnaviv_domain->stlb_cpu[i] =
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dma_alloc_coherent(etnaviv_domain->base.dev,
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SZ_4K,
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&etnaviv_domain->stlb_dma[i],
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GFP_KERNEL);
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if (!etnaviv_domain->stlb_cpu[i]) {
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ret = -ENOMEM;
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goto fail_mem;
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}
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p = etnaviv_domain->stlb_cpu[i];
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for (j = 0; j < SZ_4K / 4; j++)
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*p++ = MMUv2_PTE_EXCEPTION;
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etnaviv_domain->mtlb_cpu[i] = etnaviv_domain->stlb_dma[i] |
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MMUv2_PTE_PRESENT;
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}
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return 0;
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fail_mem:
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if (etnaviv_domain->base.bad_page_cpu)
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dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
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etnaviv_domain->base.bad_page_cpu,
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etnaviv_domain->base.bad_page_dma);
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if (etnaviv_domain->pta_cpu)
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dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
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etnaviv_domain->pta_cpu,
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etnaviv_domain->pta_dma);
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if (etnaviv_domain->mtlb_cpu)
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dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
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etnaviv_domain->mtlb_cpu,
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etnaviv_domain->mtlb_dma);
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for (i = 0; i < MMUv2_MAX_STLB_ENTRIES; i++) {
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if (etnaviv_domain->stlb_cpu[i])
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dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
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etnaviv_domain->stlb_cpu[i],
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etnaviv_domain->stlb_dma[i]);
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}
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return ret;
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}
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static void etnaviv_iommuv2_domain_free(struct etnaviv_iommu_domain *domain)
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{
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struct etnaviv_iommuv2_domain *etnaviv_domain =
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to_etnaviv_domain(domain);
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int i;
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dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
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etnaviv_domain->base.bad_page_cpu,
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etnaviv_domain->base.bad_page_dma);
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dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
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etnaviv_domain->pta_cpu,
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etnaviv_domain->pta_dma);
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dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
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etnaviv_domain->mtlb_cpu,
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etnaviv_domain->mtlb_dma);
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for (i = 0; i < MMUv2_MAX_STLB_ENTRIES; i++) {
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if (etnaviv_domain->stlb_cpu[i])
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dma_free_coherent(etnaviv_domain->base.dev, SZ_4K,
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etnaviv_domain->stlb_cpu[i],
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etnaviv_domain->stlb_dma[i]);
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}
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vfree(etnaviv_domain);
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}
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static size_t etnaviv_iommuv2_dump_size(struct etnaviv_iommu_domain *domain)
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{
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struct etnaviv_iommuv2_domain *etnaviv_domain =
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to_etnaviv_domain(domain);
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size_t dump_size = SZ_4K;
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int i;
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for (i = 0; i < MMUv2_MAX_STLB_ENTRIES; i++)
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if (etnaviv_domain->mtlb_cpu[i] & MMUv2_PTE_PRESENT)
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dump_size += SZ_4K;
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return dump_size;
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}
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static void etnaviv_iommuv2_dump(struct etnaviv_iommu_domain *domain, void *buf)
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{
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struct etnaviv_iommuv2_domain *etnaviv_domain =
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to_etnaviv_domain(domain);
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int i;
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memcpy(buf, etnaviv_domain->mtlb_cpu, SZ_4K);
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buf += SZ_4K;
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for (i = 0; i < MMUv2_MAX_STLB_ENTRIES; i++, buf += SZ_4K)
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if (etnaviv_domain->mtlb_cpu[i] & MMUv2_PTE_PRESENT)
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memcpy(buf, etnaviv_domain->stlb_cpu[i], SZ_4K);
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}
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static void etnaviv_iommuv2_restore_nonsec(struct etnaviv_gpu *gpu)
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{
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struct etnaviv_iommuv2_domain *etnaviv_domain =
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to_etnaviv_domain(gpu->mmu->domain);
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u16 prefetch;
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/* If the MMU is already enabled the state is still there. */
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if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE)
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return;
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prefetch = etnaviv_buffer_config_mmuv2(gpu,
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(u32)etnaviv_domain->mtlb_dma,
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(u32)etnaviv_domain->base.bad_page_dma);
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etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer),
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prefetch);
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etnaviv_gpu_wait_idle(gpu, 100);
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gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE);
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}
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static void etnaviv_iommuv2_restore_sec(struct etnaviv_gpu *gpu)
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{
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struct etnaviv_iommuv2_domain *etnaviv_domain =
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to_etnaviv_domain(gpu->mmu->domain);
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u16 prefetch;
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/* If the MMU is already enabled the state is still there. */
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if (gpu_read(gpu, VIVS_MMUv2_SEC_CONTROL) & VIVS_MMUv2_SEC_CONTROL_ENABLE)
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return;
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gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_LOW,
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lower_32_bits(etnaviv_domain->pta_dma));
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gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_HIGH,
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upper_32_bits(etnaviv_domain->pta_dma));
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gpu_write(gpu, VIVS_MMUv2_PTA_CONTROL, VIVS_MMUv2_PTA_CONTROL_ENABLE);
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gpu_write(gpu, VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW,
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lower_32_bits(etnaviv_domain->base.bad_page_dma));
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gpu_write(gpu, VIVS_MMUv2_SEC_SAFE_ADDR_LOW,
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lower_32_bits(etnaviv_domain->base.bad_page_dma));
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gpu_write(gpu, VIVS_MMUv2_SAFE_ADDRESS_CONFIG,
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VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH(
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upper_32_bits(etnaviv_domain->base.bad_page_dma)) |
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VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH(
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upper_32_bits(etnaviv_domain->base.bad_page_dma)));
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etnaviv_domain->pta_cpu[0] = etnaviv_domain->mtlb_dma |
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VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K;
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/* trigger a PTA load through the FE */
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prefetch = etnaviv_buffer_config_pta(gpu);
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etnaviv_gpu_start_fe(gpu, (u32)etnaviv_cmdbuf_get_pa(&gpu->buffer),
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prefetch);
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etnaviv_gpu_wait_idle(gpu, 100);
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gpu_write(gpu, VIVS_MMUv2_SEC_CONTROL, VIVS_MMUv2_SEC_CONTROL_ENABLE);
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}
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void etnaviv_iommuv2_restore(struct etnaviv_gpu *gpu)
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{
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switch (gpu->sec_mode) {
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case ETNA_SEC_NONE:
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etnaviv_iommuv2_restore_nonsec(gpu);
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break;
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case ETNA_SEC_KERNEL:
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etnaviv_iommuv2_restore_sec(gpu);
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break;
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default:
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WARN(1, "unhandled GPU security mode\n");
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break;
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}
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}
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static const struct etnaviv_iommu_domain_ops etnaviv_iommuv2_ops = {
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.free = etnaviv_iommuv2_domain_free,
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.map = etnaviv_iommuv2_map,
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.unmap = etnaviv_iommuv2_unmap,
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.dump_size = etnaviv_iommuv2_dump_size,
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.dump = etnaviv_iommuv2_dump,
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};
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struct etnaviv_iommu_domain *
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etnaviv_iommuv2_domain_alloc(struct etnaviv_gpu *gpu)
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{
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struct etnaviv_iommuv2_domain *etnaviv_domain;
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struct etnaviv_iommu_domain *domain;
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int ret;
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etnaviv_domain = vzalloc(sizeof(*etnaviv_domain));
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if (!etnaviv_domain)
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return NULL;
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domain = &etnaviv_domain->base;
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domain->dev = gpu->dev;
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domain->base = 0;
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domain->size = (u64)SZ_1G * 4;
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domain->ops = &etnaviv_iommuv2_ops;
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ret = etnaviv_iommuv2_init(etnaviv_domain);
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if (ret)
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goto out_free;
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return &etnaviv_domain->base;
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out_free:
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vfree(etnaviv_domain);
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return NULL;
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}
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