mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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bf92927251
Introduce an asm/sync.h header which provides infrastructure that can be
used to generate sync instructions of various types, and for various
reasons. For example if we need a sync instruction that provides a full
completion barrier but only on systems which have weak memory ordering,
we can generate the appropriate assembly code using:
__SYNC(full, weak_ordering)
When the kernel is configured to run on systems with weak memory
ordering (ie. CONFIG_WEAK_ORDERING is selected) we'll emit a sync
instruction. When the kernel is configured to run on systems with strong
memory ordering (ie. CONFIG_WEAK_ORDERING is not selected) we'll emit
nothing. The caller doesn't need to know which happened - it simply says
what it needs & when, with no concern for checking the kernel
configuration.
There are some scenarios in which we may want to emit code only when we
*didn't* emit a sync instruction. For example, some Loongson3 CPUs
suffer from a bug that requires us to emit a sync instruction prior to
each ll instruction (enabled by CONFIG_CPU_LOONGSON3_WORKAROUNDS). In
cases where this bug workaround is enabled, it's wasteful to then have
more generic code emit another sync instruction to provide barriers we
need in general. A __SYNC_ELSE() macro allows for this, providing an
extra argument that contains code to be assembled only in cases where
the sync instruction was not emitted. For example if we have a scenario
in which we generally want to emit a release barrier but for affected
Loongson3 configurations upgrade that to a full completion barrier, we
can do that like so:
__SYNC_ELSE(full, loongson3_war, __SYNC(rl, always))
The assembly generated by these macros can be used either as inline
assembly or in assembly source files.
Differing types of sync as provided by MIPSr6 are defined, but currently
they all generate a full completion barrier except in kernels configured
for Cavium Octeon systems. There the wmb sync-type is used, and rmb
syncs are omitted, as has been the case since commit 6b07d38aaa
("MIPS: Octeon: Use optimized memory barrier primitives."). Using
__SYNC() with the wmb or rmb types will abstract away the Octeon
specific behavior and allow us to later clean up asm/barrier.h code that
currently includes a plethora of #ifdef's.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Cc: Huacai Chen <chenhc@lemote.com>
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: linux-kernel@vger.kernel.org
739 lines
21 KiB
C
739 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2014 Imagination Technologies
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* Author: Paul Burton <paul.burton@mips.com>
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*/
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#include <linux/cpuhotplug.h>
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#include <linux/init.h>
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#include <linux/percpu.h>
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#include <linux/slab.h>
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#include <linux/suspend.h>
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#include <asm/asm-offsets.h>
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#include <asm/cacheflush.h>
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#include <asm/cacheops.h>
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#include <asm/idle.h>
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#include <asm/mips-cps.h>
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#include <asm/mipsmtregs.h>
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#include <asm/pm.h>
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#include <asm/pm-cps.h>
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#include <asm/smp-cps.h>
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#include <asm/uasm.h>
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/*
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* cps_nc_entry_fn - type of a generated non-coherent state entry function
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* @online: the count of online coupled VPEs
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* @nc_ready_count: pointer to a non-coherent mapping of the core ready_count
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*
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* The code entering & exiting non-coherent states is generated at runtime
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* using uasm, in order to ensure that the compiler cannot insert a stray
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* memory access at an unfortunate time and to allow the generation of optimal
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* core-specific code particularly for cache routines. If coupled_coherence
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* is non-zero and this is the entry function for the CPS_PM_NC_WAIT state,
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* returns the number of VPEs that were in the wait state at the point this
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* VPE left it. Returns garbage if coupled_coherence is zero or this is not
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* the entry function for CPS_PM_NC_WAIT.
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*/
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typedef unsigned (*cps_nc_entry_fn)(unsigned online, u32 *nc_ready_count);
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/*
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* The entry point of the generated non-coherent idle state entry/exit
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* functions. Actually per-core rather than per-CPU.
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*/
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static DEFINE_PER_CPU_READ_MOSTLY(cps_nc_entry_fn[CPS_PM_STATE_COUNT],
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nc_asm_enter);
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/* Bitmap indicating which states are supported by the system */
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static DECLARE_BITMAP(state_support, CPS_PM_STATE_COUNT);
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/*
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* Indicates the number of coupled VPEs ready to operate in a non-coherent
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* state. Actually per-core rather than per-CPU.
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*/
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static DEFINE_PER_CPU_ALIGNED(u32*, ready_count);
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/* Indicates online CPUs coupled with the current CPU */
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static DEFINE_PER_CPU_ALIGNED(cpumask_t, online_coupled);
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/*
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* Used to synchronize entry to deep idle states. Actually per-core rather
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* than per-CPU.
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*/
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static DEFINE_PER_CPU_ALIGNED(atomic_t, pm_barrier);
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/* Saved CPU state across the CPS_PM_POWER_GATED state */
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DEFINE_PER_CPU_ALIGNED(struct mips_static_suspend_state, cps_cpu_state);
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/* A somewhat arbitrary number of labels & relocs for uasm */
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static struct uasm_label labels[32];
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static struct uasm_reloc relocs[32];
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enum mips_reg {
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zero, at, v0, v1, a0, a1, a2, a3,
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t0, t1, t2, t3, t4, t5, t6, t7,
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s0, s1, s2, s3, s4, s5, s6, s7,
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t8, t9, k0, k1, gp, sp, fp, ra,
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};
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bool cps_pm_support_state(enum cps_pm_state state)
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{
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return test_bit(state, state_support);
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}
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static void coupled_barrier(atomic_t *a, unsigned online)
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{
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/*
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* This function is effectively the same as
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* cpuidle_coupled_parallel_barrier, which can't be used here since
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* there's no cpuidle device.
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*/
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if (!coupled_coherence)
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return;
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smp_mb__before_atomic();
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atomic_inc(a);
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while (atomic_read(a) < online)
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cpu_relax();
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if (atomic_inc_return(a) == online * 2) {
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atomic_set(a, 0);
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return;
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}
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while (atomic_read(a) > online)
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cpu_relax();
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}
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int cps_pm_enter_state(enum cps_pm_state state)
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{
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unsigned cpu = smp_processor_id();
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unsigned core = cpu_core(¤t_cpu_data);
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unsigned online, left;
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cpumask_t *coupled_mask = this_cpu_ptr(&online_coupled);
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u32 *core_ready_count, *nc_core_ready_count;
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void *nc_addr;
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cps_nc_entry_fn entry;
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struct core_boot_config *core_cfg;
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struct vpe_boot_config *vpe_cfg;
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/* Check that there is an entry function for this state */
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entry = per_cpu(nc_asm_enter, core)[state];
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if (!entry)
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return -EINVAL;
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/* Calculate which coupled CPUs (VPEs) are online */
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#if defined(CONFIG_MIPS_MT) || defined(CONFIG_CPU_MIPSR6)
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if (cpu_online(cpu)) {
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cpumask_and(coupled_mask, cpu_online_mask,
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&cpu_sibling_map[cpu]);
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online = cpumask_weight(coupled_mask);
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cpumask_clear_cpu(cpu, coupled_mask);
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} else
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#endif
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{
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cpumask_clear(coupled_mask);
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online = 1;
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}
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/* Setup the VPE to run mips_cps_pm_restore when started again */
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if (IS_ENABLED(CONFIG_CPU_PM) && state == CPS_PM_POWER_GATED) {
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/* Power gating relies upon CPS SMP */
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if (!mips_cps_smp_in_use())
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return -EINVAL;
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core_cfg = &mips_cps_core_bootcfg[core];
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vpe_cfg = &core_cfg->vpe_config[cpu_vpe_id(¤t_cpu_data)];
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vpe_cfg->pc = (unsigned long)mips_cps_pm_restore;
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vpe_cfg->gp = (unsigned long)current_thread_info();
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vpe_cfg->sp = 0;
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}
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/* Indicate that this CPU might not be coherent */
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cpumask_clear_cpu(cpu, &cpu_coherent_mask);
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smp_mb__after_atomic();
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/* Create a non-coherent mapping of the core ready_count */
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core_ready_count = per_cpu(ready_count, core);
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nc_addr = kmap_noncoherent(virt_to_page(core_ready_count),
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(unsigned long)core_ready_count);
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nc_addr += ((unsigned long)core_ready_count & ~PAGE_MASK);
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nc_core_ready_count = nc_addr;
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/* Ensure ready_count is zero-initialised before the assembly runs */
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WRITE_ONCE(*nc_core_ready_count, 0);
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coupled_barrier(&per_cpu(pm_barrier, core), online);
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/* Run the generated entry code */
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left = entry(online, nc_core_ready_count);
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/* Remove the non-coherent mapping of ready_count */
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kunmap_noncoherent();
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/* Indicate that this CPU is definitely coherent */
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cpumask_set_cpu(cpu, &cpu_coherent_mask);
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/*
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* If this VPE is the first to leave the non-coherent wait state then
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* it needs to wake up any coupled VPEs still running their wait
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* instruction so that they return to cpuidle, which can then complete
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* coordination between the coupled VPEs & provide the governor with
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* a chance to reflect on the length of time the VPEs were in the
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* idle state.
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*/
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if (coupled_coherence && (state == CPS_PM_NC_WAIT) && (left == online))
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arch_send_call_function_ipi_mask(coupled_mask);
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return 0;
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}
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static void cps_gen_cache_routine(u32 **pp, struct uasm_label **pl,
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struct uasm_reloc **pr,
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const struct cache_desc *cache,
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unsigned op, int lbl)
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{
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unsigned cache_size = cache->ways << cache->waybit;
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unsigned i;
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const unsigned unroll_lines = 32;
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/* If the cache isn't present this function has it easy */
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if (cache->flags & MIPS_CACHE_NOT_PRESENT)
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return;
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/* Load base address */
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UASM_i_LA(pp, t0, (long)CKSEG0);
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/* Calculate end address */
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if (cache_size < 0x8000)
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uasm_i_addiu(pp, t1, t0, cache_size);
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else
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UASM_i_LA(pp, t1, (long)(CKSEG0 + cache_size));
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/* Start of cache op loop */
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uasm_build_label(pl, *pp, lbl);
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/* Generate the cache ops */
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for (i = 0; i < unroll_lines; i++) {
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if (cpu_has_mips_r6) {
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uasm_i_cache(pp, op, 0, t0);
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uasm_i_addiu(pp, t0, t0, cache->linesz);
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} else {
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uasm_i_cache(pp, op, i * cache->linesz, t0);
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}
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}
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if (!cpu_has_mips_r6)
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/* Update the base address */
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uasm_i_addiu(pp, t0, t0, unroll_lines * cache->linesz);
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/* Loop if we haven't reached the end address yet */
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uasm_il_bne(pp, pr, t0, t1, lbl);
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uasm_i_nop(pp);
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}
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static int cps_gen_flush_fsb(u32 **pp, struct uasm_label **pl,
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struct uasm_reloc **pr,
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const struct cpuinfo_mips *cpu_info,
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int lbl)
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{
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unsigned i, fsb_size = 8;
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unsigned num_loads = (fsb_size * 3) / 2;
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unsigned line_stride = 2;
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unsigned line_size = cpu_info->dcache.linesz;
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unsigned perf_counter, perf_event;
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unsigned revision = cpu_info->processor_id & PRID_REV_MASK;
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/*
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* Determine whether this CPU requires an FSB flush, and if so which
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* performance counter/event reflect stalls due to a full FSB.
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*/
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switch (__get_cpu_type(cpu_info->cputype)) {
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case CPU_INTERAPTIV:
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perf_counter = 1;
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perf_event = 51;
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break;
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case CPU_PROAPTIV:
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/* Newer proAptiv cores don't require this workaround */
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if (revision >= PRID_REV_ENCODE_332(1, 1, 0))
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return 0;
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/* On older ones it's unavailable */
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return -1;
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default:
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/* Assume that the CPU does not need this workaround */
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return 0;
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}
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/*
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* Ensure that the fill/store buffer (FSB) is not holding the results
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* of a prefetch, since if it is then the CPC sequencer may become
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* stuck in the D3 (ClrBus) state whilst entering a low power state.
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*/
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/* Preserve perf counter setup */
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uasm_i_mfc0(pp, t2, 25, (perf_counter * 2) + 0); /* PerfCtlN */
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uasm_i_mfc0(pp, t3, 25, (perf_counter * 2) + 1); /* PerfCntN */
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/* Setup perf counter to count FSB full pipeline stalls */
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uasm_i_addiu(pp, t0, zero, (perf_event << 5) | 0xf);
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uasm_i_mtc0(pp, t0, 25, (perf_counter * 2) + 0); /* PerfCtlN */
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uasm_i_ehb(pp);
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uasm_i_mtc0(pp, zero, 25, (perf_counter * 2) + 1); /* PerfCntN */
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uasm_i_ehb(pp);
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/* Base address for loads */
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UASM_i_LA(pp, t0, (long)CKSEG0);
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/* Start of clear loop */
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uasm_build_label(pl, *pp, lbl);
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/* Perform some loads to fill the FSB */
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for (i = 0; i < num_loads; i++)
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uasm_i_lw(pp, zero, i * line_size * line_stride, t0);
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/*
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* Invalidate the new D-cache entries so that the cache will need
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* refilling (via the FSB) if the loop is executed again.
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*/
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for (i = 0; i < num_loads; i++) {
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uasm_i_cache(pp, Hit_Invalidate_D,
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i * line_size * line_stride, t0);
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uasm_i_cache(pp, Hit_Writeback_Inv_SD,
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i * line_size * line_stride, t0);
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}
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/* Barrier ensuring previous cache invalidates are complete */
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uasm_i_sync(pp, __SYNC_full);
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uasm_i_ehb(pp);
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/* Check whether the pipeline stalled due to the FSB being full */
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uasm_i_mfc0(pp, t1, 25, (perf_counter * 2) + 1); /* PerfCntN */
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/* Loop if it didn't */
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uasm_il_beqz(pp, pr, t1, lbl);
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uasm_i_nop(pp);
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/* Restore perf counter 1. The count may well now be wrong... */
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uasm_i_mtc0(pp, t2, 25, (perf_counter * 2) + 0); /* PerfCtlN */
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uasm_i_ehb(pp);
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uasm_i_mtc0(pp, t3, 25, (perf_counter * 2) + 1); /* PerfCntN */
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uasm_i_ehb(pp);
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return 0;
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}
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static void cps_gen_set_top_bit(u32 **pp, struct uasm_label **pl,
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struct uasm_reloc **pr,
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unsigned r_addr, int lbl)
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{
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uasm_i_lui(pp, t0, uasm_rel_hi(0x80000000));
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uasm_build_label(pl, *pp, lbl);
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uasm_i_ll(pp, t1, 0, r_addr);
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uasm_i_or(pp, t1, t1, t0);
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uasm_i_sc(pp, t1, 0, r_addr);
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uasm_il_beqz(pp, pr, t1, lbl);
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uasm_i_nop(pp);
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}
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static void *cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
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{
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struct uasm_label *l = labels;
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struct uasm_reloc *r = relocs;
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u32 *buf, *p;
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const unsigned r_online = a0;
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const unsigned r_nc_count = a1;
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const unsigned r_pcohctl = t7;
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const unsigned max_instrs = 256;
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unsigned cpc_cmd;
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int err;
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enum {
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lbl_incready = 1,
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lbl_poll_cont,
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lbl_secondary_hang,
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lbl_disable_coherence,
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lbl_flush_fsb,
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lbl_invicache,
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lbl_flushdcache,
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lbl_hang,
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lbl_set_cont,
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lbl_secondary_cont,
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lbl_decready,
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};
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/* Allocate a buffer to hold the generated code */
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p = buf = kcalloc(max_instrs, sizeof(u32), GFP_KERNEL);
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if (!buf)
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return NULL;
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/* Clear labels & relocs ready for (re)use */
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memset(labels, 0, sizeof(labels));
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memset(relocs, 0, sizeof(relocs));
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if (IS_ENABLED(CONFIG_CPU_PM) && state == CPS_PM_POWER_GATED) {
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/* Power gating relies upon CPS SMP */
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if (!mips_cps_smp_in_use())
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goto out_err;
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/*
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* Save CPU state. Note the non-standard calling convention
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* with the return address placed in v0 to avoid clobbering
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* the ra register before it is saved.
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*/
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UASM_i_LA(&p, t0, (long)mips_cps_pm_save);
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uasm_i_jalr(&p, v0, t0);
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uasm_i_nop(&p);
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}
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/*
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* Load addresses of required CM & CPC registers. This is done early
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* because they're needed in both the enable & disable coherence steps
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* but in the coupled case the enable step will only run on one VPE.
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*/
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UASM_i_LA(&p, r_pcohctl, (long)addr_gcr_cl_coherence());
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if (coupled_coherence) {
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/* Increment ready_count */
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uasm_i_sync(&p, __SYNC_mb);
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uasm_build_label(&l, p, lbl_incready);
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uasm_i_ll(&p, t1, 0, r_nc_count);
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uasm_i_addiu(&p, t2, t1, 1);
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uasm_i_sc(&p, t2, 0, r_nc_count);
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uasm_il_beqz(&p, &r, t2, lbl_incready);
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uasm_i_addiu(&p, t1, t1, 1);
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/* Barrier ensuring all CPUs see the updated r_nc_count value */
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uasm_i_sync(&p, __SYNC_mb);
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/*
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* If this is the last VPE to become ready for non-coherence
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* then it should branch below.
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*/
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uasm_il_beq(&p, &r, t1, r_online, lbl_disable_coherence);
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uasm_i_nop(&p);
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if (state < CPS_PM_POWER_GATED) {
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/*
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* Otherwise this is not the last VPE to become ready
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* for non-coherence. It needs to wait until coherence
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* has been disabled before proceeding, which it will do
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* by polling for the top bit of ready_count being set.
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*/
|
|
uasm_i_addiu(&p, t1, zero, -1);
|
|
uasm_build_label(&l, p, lbl_poll_cont);
|
|
uasm_i_lw(&p, t0, 0, r_nc_count);
|
|
uasm_il_bltz(&p, &r, t0, lbl_secondary_cont);
|
|
uasm_i_ehb(&p);
|
|
if (cpu_has_mipsmt)
|
|
uasm_i_yield(&p, zero, t1);
|
|
uasm_il_b(&p, &r, lbl_poll_cont);
|
|
uasm_i_nop(&p);
|
|
} else {
|
|
/*
|
|
* The core will lose power & this VPE will not continue
|
|
* so it can simply halt here.
|
|
*/
|
|
if (cpu_has_mipsmt) {
|
|
/* Halt the VPE via C0 tchalt register */
|
|
uasm_i_addiu(&p, t0, zero, TCHALT_H);
|
|
uasm_i_mtc0(&p, t0, 2, 4);
|
|
} else if (cpu_has_vp) {
|
|
/* Halt the VP via the CPC VP_STOP register */
|
|
unsigned int vpe_id;
|
|
|
|
vpe_id = cpu_vpe_id(&cpu_data[cpu]);
|
|
uasm_i_addiu(&p, t0, zero, 1 << vpe_id);
|
|
UASM_i_LA(&p, t1, (long)addr_cpc_cl_vp_stop());
|
|
uasm_i_sw(&p, t0, 0, t1);
|
|
} else {
|
|
BUG();
|
|
}
|
|
uasm_build_label(&l, p, lbl_secondary_hang);
|
|
uasm_il_b(&p, &r, lbl_secondary_hang);
|
|
uasm_i_nop(&p);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* This is the point of no return - this VPE will now proceed to
|
|
* disable coherence. At this point we *must* be sure that no other
|
|
* VPE within the core will interfere with the L1 dcache.
|
|
*/
|
|
uasm_build_label(&l, p, lbl_disable_coherence);
|
|
|
|
/* Invalidate the L1 icache */
|
|
cps_gen_cache_routine(&p, &l, &r, &cpu_data[cpu].icache,
|
|
Index_Invalidate_I, lbl_invicache);
|
|
|
|
/* Writeback & invalidate the L1 dcache */
|
|
cps_gen_cache_routine(&p, &l, &r, &cpu_data[cpu].dcache,
|
|
Index_Writeback_Inv_D, lbl_flushdcache);
|
|
|
|
/* Barrier ensuring previous cache invalidates are complete */
|
|
uasm_i_sync(&p, __SYNC_full);
|
|
uasm_i_ehb(&p);
|
|
|
|
if (mips_cm_revision() < CM_REV_CM3) {
|
|
/*
|
|
* Disable all but self interventions. The load from COHCTL is
|
|
* defined by the interAptiv & proAptiv SUMs as ensuring that the
|
|
* operation resulting from the preceding store is complete.
|
|
*/
|
|
uasm_i_addiu(&p, t0, zero, 1 << cpu_core(&cpu_data[cpu]));
|
|
uasm_i_sw(&p, t0, 0, r_pcohctl);
|
|
uasm_i_lw(&p, t0, 0, r_pcohctl);
|
|
|
|
/* Barrier to ensure write to coherence control is complete */
|
|
uasm_i_sync(&p, __SYNC_full);
|
|
uasm_i_ehb(&p);
|
|
}
|
|
|
|
/* Disable coherence */
|
|
uasm_i_sw(&p, zero, 0, r_pcohctl);
|
|
uasm_i_lw(&p, t0, 0, r_pcohctl);
|
|
|
|
if (state >= CPS_PM_CLOCK_GATED) {
|
|
err = cps_gen_flush_fsb(&p, &l, &r, &cpu_data[cpu],
|
|
lbl_flush_fsb);
|
|
if (err)
|
|
goto out_err;
|
|
|
|
/* Determine the CPC command to issue */
|
|
switch (state) {
|
|
case CPS_PM_CLOCK_GATED:
|
|
cpc_cmd = CPC_Cx_CMD_CLOCKOFF;
|
|
break;
|
|
case CPS_PM_POWER_GATED:
|
|
cpc_cmd = CPC_Cx_CMD_PWRDOWN;
|
|
break;
|
|
default:
|
|
BUG();
|
|
goto out_err;
|
|
}
|
|
|
|
/* Issue the CPC command */
|
|
UASM_i_LA(&p, t0, (long)addr_cpc_cl_cmd());
|
|
uasm_i_addiu(&p, t1, zero, cpc_cmd);
|
|
uasm_i_sw(&p, t1, 0, t0);
|
|
|
|
if (state == CPS_PM_POWER_GATED) {
|
|
/* If anything goes wrong just hang */
|
|
uasm_build_label(&l, p, lbl_hang);
|
|
uasm_il_b(&p, &r, lbl_hang);
|
|
uasm_i_nop(&p);
|
|
|
|
/*
|
|
* There's no point generating more code, the core is
|
|
* powered down & if powered back up will run from the
|
|
* reset vector not from here.
|
|
*/
|
|
goto gen_done;
|
|
}
|
|
|
|
/* Barrier to ensure write to CPC command is complete */
|
|
uasm_i_sync(&p, __SYNC_full);
|
|
uasm_i_ehb(&p);
|
|
}
|
|
|
|
if (state == CPS_PM_NC_WAIT) {
|
|
/*
|
|
* At this point it is safe for all VPEs to proceed with
|
|
* execution. This VPE will set the top bit of ready_count
|
|
* to indicate to the other VPEs that they may continue.
|
|
*/
|
|
if (coupled_coherence)
|
|
cps_gen_set_top_bit(&p, &l, &r, r_nc_count,
|
|
lbl_set_cont);
|
|
|
|
/*
|
|
* VPEs which did not disable coherence will continue
|
|
* executing, after coherence has been disabled, from this
|
|
* point.
|
|
*/
|
|
uasm_build_label(&l, p, lbl_secondary_cont);
|
|
|
|
/* Now perform our wait */
|
|
uasm_i_wait(&p, 0);
|
|
}
|
|
|
|
/*
|
|
* Re-enable coherence. Note that for CPS_PM_NC_WAIT all coupled VPEs
|
|
* will run this. The first will actually re-enable coherence & the
|
|
* rest will just be performing a rather unusual nop.
|
|
*/
|
|
uasm_i_addiu(&p, t0, zero, mips_cm_revision() < CM_REV_CM3
|
|
? CM_GCR_Cx_COHERENCE_COHDOMAINEN
|
|
: CM3_GCR_Cx_COHERENCE_COHEN);
|
|
|
|
uasm_i_sw(&p, t0, 0, r_pcohctl);
|
|
uasm_i_lw(&p, t0, 0, r_pcohctl);
|
|
|
|
/* Barrier to ensure write to coherence control is complete */
|
|
uasm_i_sync(&p, __SYNC_full);
|
|
uasm_i_ehb(&p);
|
|
|
|
if (coupled_coherence && (state == CPS_PM_NC_WAIT)) {
|
|
/* Decrement ready_count */
|
|
uasm_build_label(&l, p, lbl_decready);
|
|
uasm_i_sync(&p, __SYNC_mb);
|
|
uasm_i_ll(&p, t1, 0, r_nc_count);
|
|
uasm_i_addiu(&p, t2, t1, -1);
|
|
uasm_i_sc(&p, t2, 0, r_nc_count);
|
|
uasm_il_beqz(&p, &r, t2, lbl_decready);
|
|
uasm_i_andi(&p, v0, t1, (1 << fls(smp_num_siblings)) - 1);
|
|
|
|
/* Barrier ensuring all CPUs see the updated r_nc_count value */
|
|
uasm_i_sync(&p, __SYNC_mb);
|
|
}
|
|
|
|
if (coupled_coherence && (state == CPS_PM_CLOCK_GATED)) {
|
|
/*
|
|
* At this point it is safe for all VPEs to proceed with
|
|
* execution. This VPE will set the top bit of ready_count
|
|
* to indicate to the other VPEs that they may continue.
|
|
*/
|
|
cps_gen_set_top_bit(&p, &l, &r, r_nc_count, lbl_set_cont);
|
|
|
|
/*
|
|
* This core will be reliant upon another core sending a
|
|
* power-up command to the CPC in order to resume operation.
|
|
* Thus an arbitrary VPE can't trigger the core leaving the
|
|
* idle state and the one that disables coherence might as well
|
|
* be the one to re-enable it. The rest will continue from here
|
|
* after that has been done.
|
|
*/
|
|
uasm_build_label(&l, p, lbl_secondary_cont);
|
|
|
|
/* Barrier ensuring all CPUs see the updated r_nc_count value */
|
|
uasm_i_sync(&p, __SYNC_mb);
|
|
}
|
|
|
|
/* The core is coherent, time to return to C code */
|
|
uasm_i_jr(&p, ra);
|
|
uasm_i_nop(&p);
|
|
|
|
gen_done:
|
|
/* Ensure the code didn't exceed the resources allocated for it */
|
|
BUG_ON((p - buf) > max_instrs);
|
|
BUG_ON((l - labels) > ARRAY_SIZE(labels));
|
|
BUG_ON((r - relocs) > ARRAY_SIZE(relocs));
|
|
|
|
/* Patch branch offsets */
|
|
uasm_resolve_relocs(relocs, labels);
|
|
|
|
/* Flush the icache */
|
|
local_flush_icache_range((unsigned long)buf, (unsigned long)p);
|
|
|
|
return buf;
|
|
out_err:
|
|
kfree(buf);
|
|
return NULL;
|
|
}
|
|
|
|
static int cps_pm_online_cpu(unsigned int cpu)
|
|
{
|
|
enum cps_pm_state state;
|
|
unsigned core = cpu_core(&cpu_data[cpu]);
|
|
void *entry_fn, *core_rc;
|
|
|
|
for (state = CPS_PM_NC_WAIT; state < CPS_PM_STATE_COUNT; state++) {
|
|
if (per_cpu(nc_asm_enter, core)[state])
|
|
continue;
|
|
if (!test_bit(state, state_support))
|
|
continue;
|
|
|
|
entry_fn = cps_gen_entry_code(cpu, state);
|
|
if (!entry_fn) {
|
|
pr_err("Failed to generate core %u state %u entry\n",
|
|
core, state);
|
|
clear_bit(state, state_support);
|
|
}
|
|
|
|
per_cpu(nc_asm_enter, core)[state] = entry_fn;
|
|
}
|
|
|
|
if (!per_cpu(ready_count, core)) {
|
|
core_rc = kmalloc(sizeof(u32), GFP_KERNEL);
|
|
if (!core_rc) {
|
|
pr_err("Failed allocate core %u ready_count\n", core);
|
|
return -ENOMEM;
|
|
}
|
|
per_cpu(ready_count, core) = core_rc;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cps_pm_power_notifier(struct notifier_block *this,
|
|
unsigned long event, void *ptr)
|
|
{
|
|
unsigned int stat;
|
|
|
|
switch (event) {
|
|
case PM_SUSPEND_PREPARE:
|
|
stat = read_cpc_cl_stat_conf();
|
|
/*
|
|
* If we're attempting to suspend the system and power down all
|
|
* of the cores, the JTAG detect bit indicates that the CPC will
|
|
* instead put the cores into clock-off state. In this state
|
|
* a connected debugger can cause the CPU to attempt
|
|
* interactions with the powered down system. At best this will
|
|
* fail. At worst, it can hang the NoC, requiring a hard reset.
|
|
* To avoid this, just block system suspend if a JTAG probe
|
|
* is detected.
|
|
*/
|
|
if (stat & CPC_Cx_STAT_CONF_EJTAG_PROBE) {
|
|
pr_warn("JTAG probe is connected - abort suspend\n");
|
|
return NOTIFY_BAD;
|
|
}
|
|
return NOTIFY_DONE;
|
|
default:
|
|
return NOTIFY_DONE;
|
|
}
|
|
}
|
|
|
|
static int __init cps_pm_init(void)
|
|
{
|
|
/* A CM is required for all non-coherent states */
|
|
if (!mips_cm_present()) {
|
|
pr_warn("pm-cps: no CM, non-coherent states unavailable\n");
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* If interrupts were enabled whilst running a wait instruction on a
|
|
* non-coherent core then the VPE may end up processing interrupts
|
|
* whilst non-coherent. That would be bad.
|
|
*/
|
|
if (cpu_wait == r4k_wait_irqoff)
|
|
set_bit(CPS_PM_NC_WAIT, state_support);
|
|
else
|
|
pr_warn("pm-cps: non-coherent wait unavailable\n");
|
|
|
|
/* Detect whether a CPC is present */
|
|
if (mips_cpc_present()) {
|
|
/* Detect whether clock gating is implemented */
|
|
if (read_cpc_cl_stat_conf() & CPC_Cx_STAT_CONF_CLKGAT_IMPL)
|
|
set_bit(CPS_PM_CLOCK_GATED, state_support);
|
|
else
|
|
pr_warn("pm-cps: CPC does not support clock gating\n");
|
|
|
|
/* Power gating is available with CPS SMP & any CPC */
|
|
if (mips_cps_smp_in_use())
|
|
set_bit(CPS_PM_POWER_GATED, state_support);
|
|
else
|
|
pr_warn("pm-cps: CPS SMP not in use, power gating unavailable\n");
|
|
} else {
|
|
pr_warn("pm-cps: no CPC, clock & power gating unavailable\n");
|
|
}
|
|
|
|
pm_notifier(cps_pm_power_notifier, 0);
|
|
|
|
return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "mips/cps_pm:online",
|
|
cps_pm_online_cpu, NULL);
|
|
}
|
|
arch_initcall(cps_pm_init);
|