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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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5a0e3ad6af
percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
510 lines
12 KiB
C
510 lines
12 KiB
C
/*
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* Support for PCI on Celleb platform.
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*
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* (C) Copyright 2006-2007 TOSHIBA CORPORATION
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*
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* This code is based on arch/powerpc/kernel/rtas_pci.c:
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* Copyright (C) 2001 Dave Engebretsen, IBM Corporation
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* Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/threads.h>
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#include <linux/pci.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/pci_regs.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/slab.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/ppc-pci.h>
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#include "io-workarounds.h"
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#include "celleb_pci.h"
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#define MAX_PCI_DEVICES 32
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#define MAX_PCI_FUNCTIONS 8
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#define MAX_PCI_BASE_ADDRS 3 /* use 64 bit address */
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/* definition for fake pci configuration area for GbE, .... ,and etc. */
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struct celleb_pci_resource {
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struct resource r[MAX_PCI_BASE_ADDRS];
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};
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struct celleb_pci_private {
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unsigned char *fake_config[MAX_PCI_DEVICES][MAX_PCI_FUNCTIONS];
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struct celleb_pci_resource *res[MAX_PCI_DEVICES][MAX_PCI_FUNCTIONS];
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};
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static inline u8 celleb_fake_config_readb(void *addr)
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{
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u8 *p = addr;
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return *p;
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}
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static inline u16 celleb_fake_config_readw(void *addr)
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{
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__le16 *p = addr;
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return le16_to_cpu(*p);
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}
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static inline u32 celleb_fake_config_readl(void *addr)
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{
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__le32 *p = addr;
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return le32_to_cpu(*p);
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}
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static inline void celleb_fake_config_writeb(u32 val, void *addr)
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{
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u8 *p = addr;
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*p = val;
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}
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static inline void celleb_fake_config_writew(u32 val, void *addr)
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{
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__le16 val16;
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__le16 *p = addr;
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val16 = cpu_to_le16(val);
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*p = val16;
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}
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static inline void celleb_fake_config_writel(u32 val, void *addr)
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{
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__le32 val32;
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__le32 *p = addr;
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val32 = cpu_to_le32(val);
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*p = val32;
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}
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static unsigned char *get_fake_config_start(struct pci_controller *hose,
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int devno, int fn)
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{
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struct celleb_pci_private *private = hose->private_data;
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if (private == NULL)
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return NULL;
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return private->fake_config[devno][fn];
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}
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static struct celleb_pci_resource *get_resource_start(
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struct pci_controller *hose,
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int devno, int fn)
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{
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struct celleb_pci_private *private = hose->private_data;
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if (private == NULL)
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return NULL;
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return private->res[devno][fn];
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}
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static void celleb_config_read_fake(unsigned char *config, int where,
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int size, u32 *val)
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{
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char *p = config + where;
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switch (size) {
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case 1:
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*val = celleb_fake_config_readb(p);
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break;
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case 2:
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*val = celleb_fake_config_readw(p);
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break;
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case 4:
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*val = celleb_fake_config_readl(p);
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break;
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}
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}
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static void celleb_config_write_fake(unsigned char *config, int where,
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int size, u32 val)
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{
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char *p = config + where;
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switch (size) {
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case 1:
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celleb_fake_config_writeb(val, p);
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break;
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case 2:
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celleb_fake_config_writew(val, p);
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break;
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case 4:
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celleb_fake_config_writel(val, p);
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break;
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}
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}
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static int celleb_fake_pci_read_config(struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 *val)
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{
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char *config;
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struct pci_controller *hose = pci_bus_to_host(bus);
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unsigned int devno = devfn >> 3;
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unsigned int fn = devfn & 0x7;
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/* allignment check */
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BUG_ON(where % size);
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pr_debug(" fake read: bus=0x%x, ", bus->number);
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config = get_fake_config_start(hose, devno, fn);
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pr_debug("devno=0x%x, where=0x%x, size=0x%x, ", devno, where, size);
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if (!config) {
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pr_debug("failed\n");
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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celleb_config_read_fake(config, where, size, val);
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pr_debug("val=0x%x\n", *val);
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return PCIBIOS_SUCCESSFUL;
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}
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static int celleb_fake_pci_write_config(struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 val)
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{
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char *config;
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struct pci_controller *hose = pci_bus_to_host(bus);
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struct celleb_pci_resource *res;
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unsigned int devno = devfn >> 3;
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unsigned int fn = devfn & 0x7;
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/* allignment check */
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BUG_ON(where % size);
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config = get_fake_config_start(hose, devno, fn);
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if (!config)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (val == ~0) {
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int i = (where - PCI_BASE_ADDRESS_0) >> 3;
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switch (where) {
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case PCI_BASE_ADDRESS_0:
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case PCI_BASE_ADDRESS_2:
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if (size != 4)
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return PCIBIOS_DEVICE_NOT_FOUND;
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res = get_resource_start(hose, devno, fn);
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if (!res)
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return PCIBIOS_DEVICE_NOT_FOUND;
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celleb_config_write_fake(config, where, size,
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(res->r[i].end - res->r[i].start));
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return PCIBIOS_SUCCESSFUL;
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case PCI_BASE_ADDRESS_1:
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case PCI_BASE_ADDRESS_3:
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case PCI_BASE_ADDRESS_4:
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case PCI_BASE_ADDRESS_5:
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break;
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default:
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break;
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}
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}
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celleb_config_write_fake(config, where, size, val);
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pr_debug(" fake write: where=%x, size=%d, val=%x\n",
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where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops celleb_fake_pci_ops = {
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.read = celleb_fake_pci_read_config,
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.write = celleb_fake_pci_write_config,
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};
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static inline void celleb_setup_pci_base_addrs(struct pci_controller *hose,
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unsigned int devno, unsigned int fn,
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unsigned int num_base_addr)
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{
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u32 val;
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unsigned char *config;
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struct celleb_pci_resource *res;
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config = get_fake_config_start(hose, devno, fn);
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res = get_resource_start(hose, devno, fn);
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if (!config || !res)
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return;
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switch (num_base_addr) {
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case 3:
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val = (res->r[2].start & 0xfffffff0)
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| PCI_BASE_ADDRESS_MEM_TYPE_64;
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celleb_config_write_fake(config, PCI_BASE_ADDRESS_4, 4, val);
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val = res->r[2].start >> 32;
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celleb_config_write_fake(config, PCI_BASE_ADDRESS_5, 4, val);
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/* FALLTHROUGH */
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case 2:
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val = (res->r[1].start & 0xfffffff0)
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| PCI_BASE_ADDRESS_MEM_TYPE_64;
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celleb_config_write_fake(config, PCI_BASE_ADDRESS_2, 4, val);
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val = res->r[1].start >> 32;
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celleb_config_write_fake(config, PCI_BASE_ADDRESS_3, 4, val);
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/* FALLTHROUGH */
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case 1:
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val = (res->r[0].start & 0xfffffff0)
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| PCI_BASE_ADDRESS_MEM_TYPE_64;
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celleb_config_write_fake(config, PCI_BASE_ADDRESS_0, 4, val);
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val = res->r[0].start >> 32;
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celleb_config_write_fake(config, PCI_BASE_ADDRESS_1, 4, val);
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break;
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}
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val = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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celleb_config_write_fake(config, PCI_COMMAND, 2, val);
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}
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static int __init celleb_setup_fake_pci_device(struct device_node *node,
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struct pci_controller *hose)
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{
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unsigned int rlen;
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int num_base_addr = 0;
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u32 val;
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const u32 *wi0, *wi1, *wi2, *wi3, *wi4;
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unsigned int devno, fn;
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struct celleb_pci_private *private = hose->private_data;
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unsigned char **config = NULL;
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struct celleb_pci_resource **res = NULL;
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const char *name;
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const unsigned long *li;
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int size, result;
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if (private == NULL) {
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printk(KERN_ERR "PCI: "
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"memory space for pci controller is not assigned\n");
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goto error;
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}
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name = of_get_property(node, "model", &rlen);
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if (!name) {
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printk(KERN_ERR "PCI: model property not found.\n");
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goto error;
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}
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wi4 = of_get_property(node, "reg", &rlen);
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if (wi4 == NULL)
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goto error;
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devno = ((wi4[0] >> 8) & 0xff) >> 3;
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fn = (wi4[0] >> 8) & 0x7;
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pr_debug("PCI: celleb_setup_fake_pci() %s devno=%x fn=%x\n", name,
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devno, fn);
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size = 256;
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config = &private->fake_config[devno][fn];
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*config = alloc_maybe_bootmem(size, GFP_KERNEL);
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if (*config == NULL) {
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printk(KERN_ERR "PCI: "
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"not enough memory for fake configuration space\n");
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goto error;
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}
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pr_debug("PCI: fake config area assigned 0x%016lx\n",
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(unsigned long)*config);
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size = sizeof(struct celleb_pci_resource);
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res = &private->res[devno][fn];
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*res = alloc_maybe_bootmem(size, GFP_KERNEL);
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if (*res == NULL) {
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printk(KERN_ERR
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"PCI: not enough memory for resource data space\n");
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goto error;
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}
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pr_debug("PCI: res assigned 0x%016lx\n", (unsigned long)*res);
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wi0 = of_get_property(node, "device-id", NULL);
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wi1 = of_get_property(node, "vendor-id", NULL);
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wi2 = of_get_property(node, "class-code", NULL);
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wi3 = of_get_property(node, "revision-id", NULL);
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if (!wi0 || !wi1 || !wi2 || !wi3) {
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printk(KERN_ERR "PCI: Missing device tree properties.\n");
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goto error;
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}
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celleb_config_write_fake(*config, PCI_DEVICE_ID, 2, wi0[0] & 0xffff);
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celleb_config_write_fake(*config, PCI_VENDOR_ID, 2, wi1[0] & 0xffff);
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pr_debug("class-code = 0x%08x\n", wi2[0]);
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celleb_config_write_fake(*config, PCI_CLASS_PROG, 1, wi2[0] & 0xff);
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celleb_config_write_fake(*config, PCI_CLASS_DEVICE, 2,
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(wi2[0] >> 8) & 0xffff);
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celleb_config_write_fake(*config, PCI_REVISION_ID, 1, wi3[0]);
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while (num_base_addr < MAX_PCI_BASE_ADDRS) {
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result = of_address_to_resource(node,
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num_base_addr, &(*res)->r[num_base_addr]);
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if (result)
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break;
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num_base_addr++;
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}
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celleb_setup_pci_base_addrs(hose, devno, fn, num_base_addr);
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li = of_get_property(node, "interrupts", &rlen);
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if (!li) {
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printk(KERN_ERR "PCI: interrupts not found.\n");
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goto error;
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}
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val = li[0];
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celleb_config_write_fake(*config, PCI_INTERRUPT_PIN, 1, 1);
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celleb_config_write_fake(*config, PCI_INTERRUPT_LINE, 1, val);
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#ifdef DEBUG
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pr_debug("PCI: %s irq=%ld\n", name, li[0]);
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for (i = 0; i < 6; i++) {
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celleb_config_read_fake(*config,
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PCI_BASE_ADDRESS_0 + 0x4 * i, 4,
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&val);
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pr_debug("PCI: %s fn=%d base_address_%d=0x%x\n",
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name, fn, i, val);
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}
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#endif
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celleb_config_write_fake(*config, PCI_HEADER_TYPE, 1,
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PCI_HEADER_TYPE_NORMAL);
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return 0;
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error:
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if (mem_init_done) {
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if (config && *config)
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kfree(*config);
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if (res && *res)
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kfree(*res);
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} else {
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if (config && *config) {
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size = 256;
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free_bootmem((unsigned long)(*config), size);
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}
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if (res && *res) {
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size = sizeof(struct celleb_pci_resource);
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free_bootmem((unsigned long)(*res), size);
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}
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}
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return 1;
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}
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static int __init phb_set_bus_ranges(struct device_node *dev,
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struct pci_controller *phb)
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{
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const int *bus_range;
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unsigned int len;
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bus_range = of_get_property(dev, "bus-range", &len);
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if (bus_range == NULL || len < 2 * sizeof(int))
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return 1;
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phb->first_busno = bus_range[0];
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phb->last_busno = bus_range[1];
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return 0;
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}
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static void __init celleb_alloc_private_mem(struct pci_controller *hose)
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{
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hose->private_data =
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alloc_maybe_bootmem(sizeof(struct celleb_pci_private),
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GFP_KERNEL);
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}
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static int __init celleb_setup_fake_pci(struct device_node *dev,
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struct pci_controller *phb)
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{
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struct device_node *node;
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phb->ops = &celleb_fake_pci_ops;
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celleb_alloc_private_mem(phb);
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for (node = of_get_next_child(dev, NULL);
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node != NULL; node = of_get_next_child(dev, node))
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celleb_setup_fake_pci_device(node, phb);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct celleb_phb_spec celleb_fake_pci_spec __initdata = {
|
|
.setup = celleb_setup_fake_pci,
|
|
};
|
|
|
|
static struct of_device_id celleb_phb_match[] __initdata = {
|
|
{
|
|
.name = "pci-pseudo",
|
|
.data = &celleb_fake_pci_spec,
|
|
}, {
|
|
.name = "epci",
|
|
.data = &celleb_epci_spec,
|
|
}, {
|
|
.name = "pcie",
|
|
.data = &celleb_pciex_spec,
|
|
}, {
|
|
},
|
|
};
|
|
|
|
static int __init celleb_io_workaround_init(struct pci_controller *phb,
|
|
struct celleb_phb_spec *phb_spec)
|
|
{
|
|
if (phb_spec->ops) {
|
|
iowa_register_bus(phb, phb_spec->ops, phb_spec->iowa_init,
|
|
phb_spec->iowa_data);
|
|
io_workaround_init();
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int __init celleb_setup_phb(struct pci_controller *phb)
|
|
{
|
|
struct device_node *dev = phb->dn;
|
|
const struct of_device_id *match;
|
|
struct celleb_phb_spec *phb_spec;
|
|
int rc;
|
|
|
|
match = of_match_node(celleb_phb_match, dev);
|
|
if (!match)
|
|
return 1;
|
|
|
|
phb_set_bus_ranges(dev, phb);
|
|
phb->buid = 1;
|
|
|
|
phb_spec = match->data;
|
|
rc = (*phb_spec->setup)(dev, phb);
|
|
if (rc)
|
|
return 1;
|
|
|
|
return celleb_io_workaround_init(phb, phb_spec);
|
|
}
|
|
|
|
int celleb_pci_probe_mode(struct pci_bus *bus)
|
|
{
|
|
return PCI_PROBE_DEVTREE;
|
|
}
|