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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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4ccb927289
We've witnessed a few TLB events causing the machine to power off because
of prom_halt. In one case it was some nfs related area during rmmod. Another
was an mmapper of /dev/mem. A more recent one is an ITLB issue with
a bad pagesize which could be a hardware bug. Bugs happen but we should
attempt to not power off the machine and/or hang it when possible.
This is a DTLB error from an mmapper of /dev/mem:
[root@sparcie ~]# SUN4V-DTLB: Error at TPC[fffff80100903e6c], tl 1
SUN4V-DTLB: TPC<0xfffff80100903e6c>
SUN4V-DTLB: O7[fffff801081979d0]
SUN4V-DTLB: O7<0xfffff801081979d0>
SUN4V-DTLB: vaddr[fffff80100000000] ctx[1250] pte[98000000000f0610] error[2]
.
This is recent mainline for ITLB:
[ 3708.179864] SUN4V-ITLB: TPC<0xfffffc010071cefc>
[ 3708.188866] SUN4V-ITLB: O7[fffffc010071cee8]
[ 3708.197377] SUN4V-ITLB: O7<0xfffffc010071cee8>
[ 3708.206539] SUN4V-ITLB: vaddr[e0003] ctx[1a3c] pte[2900000dcc800eeb] error[4]
.
Normally sun4v_itlb_error_report() and sun4v_dtlb_error_report() would call
prom_halt() and drop us to OF command prompt "ok". This isn't the case for
LDOMs and the machine powers off.
For the HV reported error of HV_ENORADDR for HV HV_MMU_MAP_ADDR_TRAP we cause
a SIGBUS error by qualifying it within do_sparc64_fault() for fault code mask
of FAULT_CODE_BAD_RA. This is done when trap level (%tl) is less or equal
one("1"). Otherwise, for %tl > 1, we proceed eventually to die_if_kernel().
The logic of this patch was partially inspired by David Miller's feedback.
Power off of large sparc64 machines is painful. Plus die_if_kernel provides
more context. A reset sequence isn't a brief period on large sparc64 but
better than power-off/power-on sequence.
Cc: sparclinux@vger.kernel.org
Signed-off-by: Bob Picco <bob.picco@oracle.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
436 lines
10 KiB
ArmAsm
436 lines
10 KiB
ArmAsm
/* sun4v_tlb_miss.S: Sun4v TLB miss handlers.
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*
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* Copyright (C) 2006 <davem@davemloft.net>
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*/
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.text
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.align 32
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/* Load ITLB fault information into VADDR and CTX, using BASE. */
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#define LOAD_ITLB_INFO(BASE, VADDR, CTX) \
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ldx [BASE + HV_FAULT_I_ADDR_OFFSET], VADDR; \
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ldx [BASE + HV_FAULT_I_CTX_OFFSET], CTX;
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/* Load DTLB fault information into VADDR and CTX, using BASE. */
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#define LOAD_DTLB_INFO(BASE, VADDR, CTX) \
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ldx [BASE + HV_FAULT_D_ADDR_OFFSET], VADDR; \
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ldx [BASE + HV_FAULT_D_CTX_OFFSET], CTX;
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/* DEST = (VADDR >> 22)
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*
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* Branch to ZERO_CTX_LABEL if context is zero.
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*/
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#define COMPUTE_TAG_TARGET(DEST, VADDR, CTX, ZERO_CTX_LABEL) \
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srlx VADDR, 22, DEST; \
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brz,pn CTX, ZERO_CTX_LABEL; \
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nop;
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/* Create TSB pointer. This is something like:
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*
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* index_mask = (512 << (tsb_reg & 0x7UL)) - 1UL;
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* tsb_base = tsb_reg & ~0x7UL;
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* tsb_index = ((vaddr >> HASH_SHIFT) & tsb_mask);
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* tsb_ptr = tsb_base + (tsb_index * 16);
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*/
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#define COMPUTE_TSB_PTR(TSB_PTR, VADDR, HASH_SHIFT, TMP1, TMP2) \
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and TSB_PTR, 0x7, TMP1; \
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mov 512, TMP2; \
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andn TSB_PTR, 0x7, TSB_PTR; \
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sllx TMP2, TMP1, TMP2; \
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srlx VADDR, HASH_SHIFT, TMP1; \
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sub TMP2, 1, TMP2; \
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and TMP1, TMP2, TMP1; \
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sllx TMP1, 4, TMP1; \
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add TSB_PTR, TMP1, TSB_PTR;
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sun4v_itlb_miss:
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/* Load MMU Miss base into %g2. */
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ldxa [%g0] ASI_SCRATCHPAD, %g2
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/* Load UTSB reg into %g1. */
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mov SCRATCHPAD_UTSBREG1, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g1
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LOAD_ITLB_INFO(%g2, %g4, %g5)
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COMPUTE_TAG_TARGET(%g6, %g4, %g5, kvmap_itlb_4v)
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COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g3, %g7)
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/* Load TSB tag/pte into %g2/%g3 and compare the tag. */
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ldda [%g1] ASI_QUAD_LDD_PHYS_4V, %g2
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cmp %g2, %g6
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bne,a,pn %xcc, tsb_miss_page_table_walk
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mov FAULT_CODE_ITLB, %g3
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andcc %g3, _PAGE_EXEC_4V, %g0
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be,a,pn %xcc, tsb_do_fault
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mov FAULT_CODE_ITLB, %g3
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/* We have a valid entry, make hypervisor call to load
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* I-TLB and return from trap.
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*
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* %g3: PTE
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* %g4: vaddr
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*/
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sun4v_itlb_load:
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ldxa [%g0] ASI_SCRATCHPAD, %g6
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mov %o0, %g1 ! save %o0
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mov %o1, %g2 ! save %o1
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mov %o2, %g5 ! save %o2
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mov %o3, %g7 ! save %o3
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mov %g4, %o0 ! vaddr
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ldx [%g6 + HV_FAULT_I_CTX_OFFSET], %o1 ! ctx
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mov %g3, %o2 ! PTE
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mov HV_MMU_IMMU, %o3 ! flags
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ta HV_MMU_MAP_ADDR_TRAP
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brnz,pn %o0, sun4v_itlb_error
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mov %g2, %o1 ! restore %o1
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mov %g1, %o0 ! restore %o0
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mov %g5, %o2 ! restore %o2
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mov %g7, %o3 ! restore %o3
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retry
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sun4v_dtlb_miss:
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/* Load MMU Miss base into %g2. */
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ldxa [%g0] ASI_SCRATCHPAD, %g2
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/* Load UTSB reg into %g1. */
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mov SCRATCHPAD_UTSBREG1, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g1
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LOAD_DTLB_INFO(%g2, %g4, %g5)
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COMPUTE_TAG_TARGET(%g6, %g4, %g5, kvmap_dtlb_4v)
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COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g3, %g7)
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/* Load TSB tag/pte into %g2/%g3 and compare the tag. */
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ldda [%g1] ASI_QUAD_LDD_PHYS_4V, %g2
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cmp %g2, %g6
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bne,a,pn %xcc, tsb_miss_page_table_walk
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mov FAULT_CODE_DTLB, %g3
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/* We have a valid entry, make hypervisor call to load
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* D-TLB and return from trap.
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*
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* %g3: PTE
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* %g4: vaddr
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*/
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sun4v_dtlb_load:
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ldxa [%g0] ASI_SCRATCHPAD, %g6
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mov %o0, %g1 ! save %o0
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mov %o1, %g2 ! save %o1
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mov %o2, %g5 ! save %o2
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mov %o3, %g7 ! save %o3
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mov %g4, %o0 ! vaddr
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ldx [%g6 + HV_FAULT_D_CTX_OFFSET], %o1 ! ctx
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mov %g3, %o2 ! PTE
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mov HV_MMU_DMMU, %o3 ! flags
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ta HV_MMU_MAP_ADDR_TRAP
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brnz,pn %o0, sun4v_dtlb_error
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mov %g2, %o1 ! restore %o1
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mov %g1, %o0 ! restore %o0
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mov %g5, %o2 ! restore %o2
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mov %g7, %o3 ! restore %o3
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retry
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sun4v_dtlb_prot:
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SET_GL(1)
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/* Load MMU Miss base into %g5. */
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ldxa [%g0] ASI_SCRATCHPAD, %g5
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ldx [%g5 + HV_FAULT_D_ADDR_OFFSET], %g5
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rdpr %tl, %g1
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cmp %g1, 1
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bgu,pn %xcc, winfix_trampoline
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mov FAULT_CODE_DTLB | FAULT_CODE_WRITE, %g4
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ba,pt %xcc, sparc64_realfault_common
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nop
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/* Called from trap table:
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* %g4: vaddr
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* %g5: context
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* %g6: TAG TARGET
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*/
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sun4v_itsb_miss:
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mov SCRATCHPAD_UTSBREG1, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g1
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brz,pn %g5, kvmap_itlb_4v
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mov FAULT_CODE_ITLB, %g3
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ba,a,pt %xcc, sun4v_tsb_miss_common
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/* Called from trap table:
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* %g4: vaddr
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* %g5: context
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* %g6: TAG TARGET
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*/
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sun4v_dtsb_miss:
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mov SCRATCHPAD_UTSBREG1, %g1
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ldxa [%g1] ASI_SCRATCHPAD, %g1
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brz,pn %g5, kvmap_dtlb_4v
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mov FAULT_CODE_DTLB, %g3
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/* fallthrough */
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sun4v_tsb_miss_common:
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COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g5, %g7)
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sub %g2, TRAP_PER_CPU_FAULT_INFO, %g2
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#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
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mov SCRATCHPAD_UTSBREG2, %g5
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ldxa [%g5] ASI_SCRATCHPAD, %g5
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cmp %g5, -1
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be,pt %xcc, 80f
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nop
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COMPUTE_TSB_PTR(%g5, %g4, REAL_HPAGE_SHIFT, %g2, %g7)
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/* That clobbered %g2, reload it. */
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ldxa [%g0] ASI_SCRATCHPAD, %g2
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sub %g2, TRAP_PER_CPU_FAULT_INFO, %g2
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80: stx %g5, [%g2 + TRAP_PER_CPU_TSB_HUGE_TEMP]
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#endif
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ba,pt %xcc, tsb_miss_page_table_walk_sun4v_fastpath
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ldx [%g2 + TRAP_PER_CPU_PGD_PADDR], %g7
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sun4v_itlb_error:
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rdpr %tl, %g1
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cmp %g1, 1
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ble,pt %icc, sun4v_bad_ra
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or %g0, FAULT_CODE_BAD_RA | FAULT_CODE_ITLB, %g1
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sethi %hi(sun4v_err_itlb_vaddr), %g1
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stx %g4, [%g1 + %lo(sun4v_err_itlb_vaddr)]
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sethi %hi(sun4v_err_itlb_ctx), %g1
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ldxa [%g0] ASI_SCRATCHPAD, %g6
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ldx [%g6 + HV_FAULT_I_CTX_OFFSET], %o1
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stx %o1, [%g1 + %lo(sun4v_err_itlb_ctx)]
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sethi %hi(sun4v_err_itlb_pte), %g1
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stx %g3, [%g1 + %lo(sun4v_err_itlb_pte)]
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sethi %hi(sun4v_err_itlb_error), %g1
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stx %o0, [%g1 + %lo(sun4v_err_itlb_error)]
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sethi %hi(1f), %g7
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rdpr %tl, %g4
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ba,pt %xcc, etraptl1
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1: or %g7, %lo(1f), %g7
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mov %l4, %o1
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call sun4v_itlb_error_report
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add %sp, PTREGS_OFF, %o0
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/* NOTREACHED */
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sun4v_dtlb_error:
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rdpr %tl, %g1
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cmp %g1, 1
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ble,pt %icc, sun4v_bad_ra
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or %g0, FAULT_CODE_BAD_RA | FAULT_CODE_DTLB, %g1
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sethi %hi(sun4v_err_dtlb_vaddr), %g1
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stx %g4, [%g1 + %lo(sun4v_err_dtlb_vaddr)]
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sethi %hi(sun4v_err_dtlb_ctx), %g1
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ldxa [%g0] ASI_SCRATCHPAD, %g6
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ldx [%g6 + HV_FAULT_D_CTX_OFFSET], %o1
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stx %o1, [%g1 + %lo(sun4v_err_dtlb_ctx)]
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sethi %hi(sun4v_err_dtlb_pte), %g1
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stx %g3, [%g1 + %lo(sun4v_err_dtlb_pte)]
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sethi %hi(sun4v_err_dtlb_error), %g1
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stx %o0, [%g1 + %lo(sun4v_err_dtlb_error)]
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sethi %hi(1f), %g7
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rdpr %tl, %g4
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ba,pt %xcc, etraptl1
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1: or %g7, %lo(1f), %g7
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mov %l4, %o1
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call sun4v_dtlb_error_report
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add %sp, PTREGS_OFF, %o0
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/* NOTREACHED */
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sun4v_bad_ra:
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or %g0, %g4, %g5
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ba,pt %xcc, sparc64_realfault_common
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or %g1, %g0, %g4
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/* NOTREACHED */
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/* Instruction Access Exception, tl0. */
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sun4v_iacc:
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ldxa [%g0] ASI_SCRATCHPAD, %g2
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ldx [%g2 + HV_FAULT_I_TYPE_OFFSET], %g3
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ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4
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ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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ba,pt %xcc, etrap
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rd %pc, %g7
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mov %l4, %o1
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mov %l5, %o2
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call sun4v_insn_access_exception
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap
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/* Instruction Access Exception, tl1. */
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sun4v_iacc_tl1:
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ldxa [%g0] ASI_SCRATCHPAD, %g2
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ldx [%g2 + HV_FAULT_I_TYPE_OFFSET], %g3
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ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4
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ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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ba,pt %xcc, etraptl1
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rd %pc, %g7
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mov %l4, %o1
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mov %l5, %o2
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call sun4v_insn_access_exception_tl1
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap
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/* Data Access Exception, tl0. */
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sun4v_dacc:
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ldxa [%g0] ASI_SCRATCHPAD, %g2
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ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
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ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
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ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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ba,pt %xcc, etrap
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rd %pc, %g7
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mov %l4, %o1
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mov %l5, %o2
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call sun4v_data_access_exception
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap
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/* Data Access Exception, tl1. */
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sun4v_dacc_tl1:
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ldxa [%g0] ASI_SCRATCHPAD, %g2
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ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
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ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
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ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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ba,pt %xcc, etraptl1
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rd %pc, %g7
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mov %l4, %o1
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mov %l5, %o2
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call sun4v_data_access_exception_tl1
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap
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/* Memory Address Unaligned. */
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sun4v_mna:
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/* Window fixup? */
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rdpr %tl, %g2
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cmp %g2, 1
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ble,pt %icc, 1f
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nop
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SET_GL(1)
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ldxa [%g0] ASI_SCRATCHPAD, %g2
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ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g5
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mov HV_FAULT_TYPE_UNALIGNED, %g3
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ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g4
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sllx %g3, 16, %g3
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or %g4, %g3, %g4
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ba,pt %xcc, winfix_mna
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rdpr %tpc, %g3
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/* not reached */
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1: ldxa [%g0] ASI_SCRATCHPAD, %g2
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mov HV_FAULT_TYPE_UNALIGNED, %g3
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ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
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ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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ba,pt %xcc, etrap
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rd %pc, %g7
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mov %l4, %o1
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mov %l5, %o2
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call sun4v_do_mna
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap
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/* Privileged Action. */
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sun4v_privact:
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ba,pt %xcc, etrap
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rd %pc, %g7
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call do_privact
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap
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/* Unaligned ldd float, tl0. */
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sun4v_lddfmna:
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ldxa [%g0] ASI_SCRATCHPAD, %g2
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ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
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ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
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ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
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sllx %g3, 16, %g3
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or %g5, %g3, %g5
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ba,pt %xcc, etrap
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rd %pc, %g7
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mov %l4, %o1
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mov %l5, %o2
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call handle_lddfmna
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap
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/* Unaligned std float, tl0. */
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sun4v_stdfmna:
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ldxa [%g0] ASI_SCRATCHPAD, %g2
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ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
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ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
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ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
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|
sllx %g3, 16, %g3
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|
or %g5, %g3, %g5
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|
ba,pt %xcc, etrap
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|
rd %pc, %g7
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|
mov %l4, %o1
|
|
mov %l5, %o2
|
|
call handle_stdfmna
|
|
add %sp, PTREGS_OFF, %o0
|
|
ba,a,pt %xcc, rtrap
|
|
|
|
#define BRANCH_ALWAYS 0x10680000
|
|
#define NOP 0x01000000
|
|
#define SUN4V_DO_PATCH(OLD, NEW) \
|
|
sethi %hi(NEW), %g1; \
|
|
or %g1, %lo(NEW), %g1; \
|
|
sethi %hi(OLD), %g2; \
|
|
or %g2, %lo(OLD), %g2; \
|
|
sub %g1, %g2, %g1; \
|
|
sethi %hi(BRANCH_ALWAYS), %g3; \
|
|
sll %g1, 11, %g1; \
|
|
srl %g1, 11 + 2, %g1; \
|
|
or %g3, %lo(BRANCH_ALWAYS), %g3; \
|
|
or %g3, %g1, %g3; \
|
|
stw %g3, [%g2]; \
|
|
sethi %hi(NOP), %g3; \
|
|
or %g3, %lo(NOP), %g3; \
|
|
stw %g3, [%g2 + 0x4]; \
|
|
flush %g2;
|
|
|
|
.globl sun4v_patch_tlb_handlers
|
|
.type sun4v_patch_tlb_handlers,#function
|
|
sun4v_patch_tlb_handlers:
|
|
SUN4V_DO_PATCH(tl0_iamiss, sun4v_itlb_miss)
|
|
SUN4V_DO_PATCH(tl1_iamiss, sun4v_itlb_miss)
|
|
SUN4V_DO_PATCH(tl0_damiss, sun4v_dtlb_miss)
|
|
SUN4V_DO_PATCH(tl1_damiss, sun4v_dtlb_miss)
|
|
SUN4V_DO_PATCH(tl0_daprot, sun4v_dtlb_prot)
|
|
SUN4V_DO_PATCH(tl1_daprot, sun4v_dtlb_prot)
|
|
SUN4V_DO_PATCH(tl0_iax, sun4v_iacc)
|
|
SUN4V_DO_PATCH(tl1_iax, sun4v_iacc_tl1)
|
|
SUN4V_DO_PATCH(tl0_dax, sun4v_dacc)
|
|
SUN4V_DO_PATCH(tl1_dax, sun4v_dacc_tl1)
|
|
SUN4V_DO_PATCH(tl0_mna, sun4v_mna)
|
|
SUN4V_DO_PATCH(tl1_mna, sun4v_mna)
|
|
SUN4V_DO_PATCH(tl0_lddfmna, sun4v_lddfmna)
|
|
SUN4V_DO_PATCH(tl0_stdfmna, sun4v_stdfmna)
|
|
SUN4V_DO_PATCH(tl0_privact, sun4v_privact)
|
|
retl
|
|
nop
|
|
.size sun4v_patch_tlb_handlers,.-sun4v_patch_tlb_handlers
|