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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1d5e83aac5
The Vitesse 824x PHY doesn't allow an interrupt to be cleared if the mask bit for that interrupt isn't set. This means that the PHY Lib's order of handling interrupts (disable, then clear) breaks on this PHY. However, clearing then disabling the interrupt opens up the code for a silly race condition. So rather than change the PHY Lib, we change the Vitesse driver so it always clears interrupts before disabling them. Further, the ack function only clears the interrupt if interrupts are enabled. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Acked-by: Haiying Wang <Haiying.Wang@freescale.com>
131 lines
3.2 KiB
C
131 lines
3.2 KiB
C
/*
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* Driver for Vitesse PHYs
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*
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* Author: Kriston Carson
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*
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* Copyright (c) 2005 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/phy.h>
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/* Vitesse Extended Control Register 1 */
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#define MII_VSC8244_EXT_CON1 0x17
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#define MII_VSC8244_EXTCON1_INIT 0x0000
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/* Vitesse Interrupt Mask Register */
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#define MII_VSC8244_IMASK 0x19
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#define MII_VSC8244_IMASK_IEN 0x8000
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#define MII_VSC8244_IMASK_SPEED 0x4000
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#define MII_VSC8244_IMASK_LINK 0x2000
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#define MII_VSC8244_IMASK_DUPLEX 0x1000
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#define MII_VSC8244_IMASK_MASK 0xf000
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/* Vitesse Interrupt Status Register */
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#define MII_VSC8244_ISTAT 0x1a
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#define MII_VSC8244_ISTAT_STATUS 0x8000
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#define MII_VSC8244_ISTAT_SPEED 0x4000
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#define MII_VSC8244_ISTAT_LINK 0x2000
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#define MII_VSC8244_ISTAT_DUPLEX 0x1000
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/* Vitesse Auxiliary Control/Status Register */
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#define MII_VSC8244_AUX_CONSTAT 0x1c
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#define MII_VSC8244_AUXCONSTAT_INIT 0x0004
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#define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020
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#define MII_VSC8244_AUXCONSTAT_SPEED 0x0018
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#define MII_VSC8244_AUXCONSTAT_GBIT 0x0010
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#define MII_VSC8244_AUXCONSTAT_100 0x0008
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MODULE_DESCRIPTION("Vitesse PHY driver");
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MODULE_AUTHOR("Kriston Carson");
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MODULE_LICENSE("GPL");
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static int vsc824x_config_init(struct phy_device *phydev)
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{
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int err;
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err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
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MII_VSC8244_AUXCONSTAT_INIT);
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if (err < 0)
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return err;
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err = phy_write(phydev, MII_VSC8244_EXT_CON1,
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MII_VSC8244_EXTCON1_INIT);
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return err;
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}
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static int vsc824x_ack_interrupt(struct phy_device *phydev)
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{
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int err = 0;
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/*
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* Don't bother to ACK the interrupts if interrupts
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* are disabled. The 824x cannot clear the interrupts
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* if they are disabled.
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*/
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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err = phy_read(phydev, MII_VSC8244_ISTAT);
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return (err < 0) ? err : 0;
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}
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static int vsc824x_config_intr(struct phy_device *phydev)
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{
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int err;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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err = phy_write(phydev, MII_VSC8244_IMASK,
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MII_VSC8244_IMASK_MASK);
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else {
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/*
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* The Vitesse PHY cannot clear the interrupt
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* once it has disabled them, so we clear them first
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*/
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err = phy_read(phydev, MII_VSC8244_ISTAT);
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if (err)
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return err;
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err = phy_write(phydev, MII_VSC8244_IMASK, 0);
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}
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return err;
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}
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/* Vitesse 824x */
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static struct phy_driver vsc8244_driver = {
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.phy_id = 0x000fc6c0,
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.name = "Vitesse VSC8244",
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.phy_id_mask = 0x000fffc0,
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.features = PHY_GBIT_FEATURES,
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.flags = PHY_HAS_INTERRUPT,
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.config_init = &vsc824x_config_init,
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.config_aneg = &genphy_config_aneg,
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.read_status = &genphy_read_status,
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.ack_interrupt = &vsc824x_ack_interrupt,
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.config_intr = &vsc824x_config_intr,
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.driver = { .owner = THIS_MODULE,},
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};
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static int __init vsc8244_init(void)
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{
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return phy_driver_register(&vsc8244_driver);
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}
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static void __exit vsc8244_exit(void)
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{
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phy_driver_unregister(&vsc8244_driver);
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}
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module_init(vsc8244_init);
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module_exit(vsc8244_exit);
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