mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 19:20:55 +07:00
c641d4dfef
This revamps the device tree to fit with the new clock implementation and brings it quite a bit closer to how the hardware actually works. After this the clock implementation knows about all clock gates and will gate off all unused clocks at boot time and save a bit of power. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
825 lines
18 KiB
Plaintext
825 lines
18 KiB
Plaintext
/*
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* Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC
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*/
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/include/ "skeleton.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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memory {
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reg = <0x00000000 0x04000000>,
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<0x08000000 0x04000000>;
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};
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L2: l2-cache {
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compatible = "arm,l210-cache";
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reg = <0x10210000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <30>;
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cache-unified;
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cache-level = <2>;
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};
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mtu0: mtu@101e2000 {
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/* Nomadik system timer */
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compatible = "st,nomadik-mtu";
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reg = <0x101e2000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <4>;
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clocks = <&timclk>, <&pclk>;
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clock-names = "timclk", "apb_pclk";
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};
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mtu1: mtu@101e3000 {
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/* Secondary timer */
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reg = <0x101e3000 0x1000>;
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interrupt-parent = <&vica>;
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interrupts = <5>;
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clocks = <&timclk>, <&pclk>;
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clock-names = "timclk", "apb_pclk";
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};
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gpio0: gpio@101e4000 {
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compatible = "st,nomadik-gpio";
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reg = <0x101e4000 0x80>;
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interrupt-parent = <&vica>;
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interrupts = <6>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-bank = <0>;
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clocks = <&pclk>;
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};
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gpio1: gpio@101e5000 {
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compatible = "st,nomadik-gpio";
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reg = <0x101e5000 0x80>;
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interrupt-parent = <&vica>;
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interrupts = <7>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-bank = <1>;
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clocks = <&pclk>;
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};
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gpio2: gpio@101e6000 {
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compatible = "st,nomadik-gpio";
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reg = <0x101e6000 0x80>;
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interrupt-parent = <&vica>;
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interrupts = <8>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-bank = <2>;
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clocks = <&pclk>;
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};
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gpio3: gpio@101e7000 {
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compatible = "st,nomadik-gpio";
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reg = <0x101e7000 0x80>;
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interrupt-parent = <&vica>;
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interrupts = <9>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-bank = <3>;
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clocks = <&pclk>;
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};
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pinctrl {
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compatible = "stericsson,stn8815-pinctrl";
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/* Pin configurations */
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uart0 {
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uart0_default_mux: uart0_mux {
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u0_default_mux {
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ste,function = "u0";
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ste,pins = "u0_a_1";
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};
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};
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};
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uart1 {
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uart1_default_mux: uart1_mux {
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u1_default_mux {
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ste,function = "u1";
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ste,pins = "u1_a_1";
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};
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};
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};
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mmcsd {
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mmcsd_default_mux: mmcsd_mux {
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mmcsd_default_mux {
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ste,function = "mmcsd";
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ste,pins = "mmcsd_a_1";
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};
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};
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mmcsd_default_mode: mmcsd_default {
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mmcsd_default_cfg1 {
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/* MCCLK */
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ste,pins = "GPIO8_B10";
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ste,output = <0>;
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};
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mmcsd_default_cfg2 {
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/* MCCMDDIR, MCDAT0DIR, MCDAT31DIR */
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ste,pins = "GPIO10_C11", "GPIO15_A12",
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"GPIO16_C13";
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ste,output = <1>;
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};
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mmcsd_default_cfg3 {
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/* MCCMD, MCDAT3-0, MCMSFBCLK */
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ste,pins = "GPIO9_A10", "GPIO11_B11",
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"GPIO12_A11", "GPIO13_C12",
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"GPIO14_B12", "GPIO24_C15";
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ste,input = <1>;
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};
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};
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};
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i2c0 {
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i2c0_default_mode: i2c0_default {
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i2c0_default_cfg {
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ste,pins = "GPIO62_D3", "GPIO63_D2";
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ste,input = <1>;
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};
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};
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};
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i2c1 {
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i2c1_default_mode: i2c1_default {
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i2c1_default_cfg {
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ste,pins = "GPIO53_L4", "GPIO54_L3";
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ste,input = <1>;
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};
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};
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};
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i2c2 {
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i2c2_default_mode: i2c2_default {
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i2c2_default_cfg {
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ste,pins = "GPIO73_C21", "GPIO74_C20";
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ste,input = <1>;
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};
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};
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};
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};
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src: src@101e0000 {
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compatible = "stericsson,nomadik-src";
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reg = <0x101e0000 0x1000>;
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disable-sxtalo;
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disable-mxtalo;
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/*
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* MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz
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* that is parent of TIMCLK, PLL1 and PLL2
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*/
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mxtal: mxtal@19.2M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <19200000>;
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};
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/*
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* The 2.4 MHz TIMCLK reference clock is active at
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* boot time, this is actually the MXTALCLK @19.2 MHz
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* divided by 8. This clock is used by the timers and
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* watchdog. See page 105 ff.
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*/
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timclk: timclk@2.4M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <8>;
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clock-mult = <1>;
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clocks = <&mxtal>;
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};
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/* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
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pll1: pll1@0 {
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#clock-cells = <0>;
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compatible = "st,nomadik-pll-clock";
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pll-id = <1>;
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clocks = <&mxtal>;
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};
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/* HCLK divides the PLL1 with 1,2,3 or 4 */
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hclk: hclk@0 {
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#clock-cells = <0>;
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compatible = "st,nomadik-hclk-clock";
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clocks = <&pll1>;
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};
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/* The PCLK domain uses HCLK right off */
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pclk: pclk@0 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&hclk>;
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};
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/* PLL2 is usually 864 MHz and divided into a few fixed rates */
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pll2: pll2@0 {
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#clock-cells = <0>;
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compatible = "st,nomadik-pll-clock";
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pll-id = <2>;
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clocks = <&mxtal>;
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};
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clk216: clk216@216M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <4>;
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clock-mult = <1>;
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clocks = <&pll2>;
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};
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clk108: clk108@108M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <2>;
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clock-mult = <1>;
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clocks = <&clk216>;
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};
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clk72: clk72@72M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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/* The data sheet does not say how this is derived */
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clock-div = <12>;
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clock-mult = <1>;
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clocks = <&pll2>;
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};
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clk48: clk48@48M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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/* The data sheet does not say how this is derived */
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clock-div = <18>;
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clock-mult = <1>;
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clocks = <&pll2>;
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};
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clk27: clk27@27M {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <4>;
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clock-mult = <1>;
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clocks = <&clk108>;
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};
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/* This apparently exists as well */
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ulpiclk: ulpiclk@60M {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <60000000>;
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};
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/*
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* IP AMBA bus clocks, driving the bus side of the
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* peripheral clocking, clock gates.
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*/
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hclkdma0: hclkdma0@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <0>;
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clocks = <&hclk>;
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};
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hclksmc: hclksmc@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <1>;
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clocks = <&hclk>;
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};
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hclksdram: hclksdram@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <2>;
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clocks = <&hclk>;
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};
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hclkdma1: hclkdma1@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <3>;
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clocks = <&hclk>;
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};
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hclkclcd: hclkclcd@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <4>;
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clocks = <&hclk>;
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};
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pclkirda: pclkirda@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <5>;
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clocks = <&pclk>;
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};
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pclkssp: pclkssp@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <6>;
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clocks = <&pclk>;
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};
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pclkuart0: pclkuart0@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <7>;
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clocks = <&pclk>;
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};
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pclksdi: pclksdi@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <8>;
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clocks = <&pclk>;
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};
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pclki2c0: pclki2c0@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <9>;
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clocks = <&pclk>;
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};
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pclki2c1: pclki2c1@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <10>;
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clocks = <&pclk>;
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};
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pclkuart1: pclkuart1@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <11>;
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clocks = <&pclk>;
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};
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pclkmsp0: pclkmsp0@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <12>;
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clocks = <&pclk>;
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};
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hclkusb: hclkusb@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <13>;
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clocks = <&hclk>;
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};
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hclkdif: hclkdif@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <14>;
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clocks = <&hclk>;
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};
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hclksaa: hclksaa@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <15>;
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clocks = <&hclk>;
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};
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hclksva: hclksva@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <16>;
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clocks = <&hclk>;
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};
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pclkhsi: pclkhsi@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <17>;
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clocks = <&pclk>;
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};
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pclkxti: pclkxti@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <18>;
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clocks = <&pclk>;
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};
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pclkuart2: pclkuart2@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <19>;
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clocks = <&pclk>;
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};
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pclkmsp1: pclkmsp1@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <20>;
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clocks = <&pclk>;
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};
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pclkmsp2: pclkmsp2@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <21>;
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clocks = <&pclk>;
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};
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pclkowm: pclkowm@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <22>;
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clocks = <&pclk>;
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};
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hclkhpi: hclkhpi@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <23>;
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clocks = <&hclk>;
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};
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pclkske: pclkske@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <24>;
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clocks = <&pclk>;
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};
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pclkhsem: pclkhsem@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <25>;
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clocks = <&pclk>;
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};
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hclk3d: hclk3d@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <26>;
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clocks = <&hclk>;
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};
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hclkhash: hclkhash@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <27>;
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clocks = <&hclk>;
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};
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hclkcryp: hclkcryp@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <28>;
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clocks = <&hclk>;
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};
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pclkmshc: pclkmshc@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <29>;
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clocks = <&pclk>;
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};
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hclkusbm: hclkusbm@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <30>;
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clocks = <&hclk>;
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};
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hclkrng: hclkrng@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <31>;
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clocks = <&hclk>;
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};
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/* IP kernel clocks */
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clcdclk: clcdclk@0 {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <36>;
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clocks = <&clk72 &clk48>;
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};
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irdaclk: irdaclk@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <37>;
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clocks = <&clk48>;
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};
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sspiclk: sspiclk@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <38>;
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clocks = <&clk48>;
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};
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uart0clk: uart0clk@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <39>;
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clocks = <&clk48>;
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};
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sdiclk: sdiclk@48M {
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/* Also called MCCLK in some documents */
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <40>;
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clocks = <&clk48>;
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};
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i2c0clk: i2c0clk@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <41>;
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clocks = <&clk48>;
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};
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i2c1clk: i2c1clk@48M {
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#clock-cells = <0>;
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compatible = "st,nomadik-src-clock";
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clock-id = <42>;
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clocks = <&clk48>;
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};
|
|
uart1clk: uart1clk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <43>;
|
|
clocks = <&clk48>;
|
|
};
|
|
mspclk0: mspclk0@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <44>;
|
|
clocks = <&clk48>;
|
|
};
|
|
usbclk: usbclk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <45>;
|
|
clocks = <&clk48>; /* 48 MHz not ULPI */
|
|
};
|
|
difclk: difclk@72M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <46>;
|
|
clocks = <&clk72>;
|
|
};
|
|
ipi2cclk: ipi2cclk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <47>;
|
|
clocks = <&clk48>; /* Guess */
|
|
};
|
|
ipbmcclk: ipbmcclk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <48>;
|
|
clocks = <&clk48>; /* Guess */
|
|
};
|
|
hsiclkrx: hsiclkrx@216M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <49>;
|
|
clocks = <&clk216>;
|
|
};
|
|
hsiclktx: hsiclktx@108M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <50>;
|
|
clocks = <&clk108>;
|
|
};
|
|
uart2clk: uart2clk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <51>;
|
|
clocks = <&clk48>;
|
|
};
|
|
mspclk1: mspclk1@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <52>;
|
|
clocks = <&clk48>;
|
|
};
|
|
mspclk2: mspclk2@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <53>;
|
|
clocks = <&clk48>;
|
|
};
|
|
owmclk: owmclk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <54>;
|
|
clocks = <&clk48>; /* Guess */
|
|
};
|
|
skeclk: skeclk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <56>;
|
|
clocks = <&clk48>; /* Guess */
|
|
};
|
|
x3dclk: x3dclk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <58>;
|
|
clocks = <&clk48>; /* Guess */
|
|
};
|
|
pclkmsp3: pclkmsp3@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <59>;
|
|
clocks = <&pclk>;
|
|
};
|
|
mspclk3: mspclk3@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <60>;
|
|
clocks = <&clk48>;
|
|
};
|
|
mshcclk: mshcclk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <61>;
|
|
clocks = <&clk48>; /* Guess */
|
|
};
|
|
usbmclk: usbmclk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <62>;
|
|
/* Stated as "48 MHz not ULPI clock" */
|
|
clocks = <&clk48>;
|
|
};
|
|
rngcclk: rngcclk@48M {
|
|
#clock-cells = <0>;
|
|
compatible = "st,nomadik-src-clock";
|
|
clock-id = <63>;
|
|
clocks = <&clk48>; /* Guess */
|
|
};
|
|
};
|
|
|
|
/* A NAND flash of 128 MiB */
|
|
fsmc: flash@40000000 {
|
|
compatible = "stericsson,fsmc-nand";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x10100000 0x1000>, /* FSMC Register*/
|
|
<0x40000000 0x2000>, /* NAND Base DATA */
|
|
<0x41000000 0x2000>, /* NAND Base ADDR */
|
|
<0x40800000 0x2000>; /* NAND Base CMD */
|
|
reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
|
|
clocks = <&hclksmc>;
|
|
status = "okay";
|
|
|
|
partition@0 {
|
|
label = "X-Loader(NAND)";
|
|
reg = <0x0 0x40000>;
|
|
};
|
|
partition@40000 {
|
|
label = "MemInit(NAND)";
|
|
reg = <0x40000 0x40000>;
|
|
};
|
|
partition@80000 {
|
|
label = "BootLoader(NAND)";
|
|
reg = <0x80000 0x200000>;
|
|
};
|
|
partition@280000 {
|
|
label = "Kernel zImage(NAND)";
|
|
reg = <0x280000 0x300000>;
|
|
};
|
|
partition@580000 {
|
|
label = "Root Filesystem(NAND)";
|
|
reg = <0x580000 0x1600000>;
|
|
};
|
|
partition@1b80000 {
|
|
label = "User Filesystem(NAND)";
|
|
reg = <0x1b80000 0x6480000>;
|
|
};
|
|
};
|
|
|
|
external-bus@34000000 {
|
|
compatible = "simple-bus";
|
|
reg = <0x34000000 0x1000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x34000000 0x1000000>;
|
|
ethernet@300 {
|
|
compatible = "smsc,lan91c111";
|
|
reg = <0x300 0x0fd00>;
|
|
};
|
|
};
|
|
|
|
/* I2C0 connected to the STw4811 power management chip */
|
|
i2c0 {
|
|
compatible = "i2c-gpio";
|
|
gpios = <&gpio1 31 0>, /* sda */
|
|
<&gpio1 30 0>; /* scl */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_default_mode>;
|
|
|
|
stw4811@2d {
|
|
compatible = "st,stw4811";
|
|
reg = <0x2d>;
|
|
};
|
|
};
|
|
|
|
/* I2C1 connected to various sensors */
|
|
i2c1 {
|
|
compatible = "i2c-gpio";
|
|
gpios = <&gpio1 22 0>, /* sda */
|
|
<&gpio1 21 0>; /* scl */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_default_mode>;
|
|
|
|
camera@2d {
|
|
compatible = "st,camera";
|
|
reg = <0x10>;
|
|
};
|
|
stw5095@1a {
|
|
compatible = "st,stw5095";
|
|
reg = <0x1a>;
|
|
};
|
|
lis3lv02dl@1d {
|
|
compatible = "st,lis3lv02dl";
|
|
reg = <0x1d>;
|
|
};
|
|
};
|
|
|
|
/* I2C2 connected to the USB portions of the STw4811 only */
|
|
i2c2 {
|
|
compatible = "i2c-gpio";
|
|
gpios = <&gpio2 10 0>, /* sda */
|
|
<&gpio2 9 0>; /* scl */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_default_mode>;
|
|
|
|
stw4811@2d {
|
|
compatible = "st,stw4811-usb";
|
|
reg = <0x2d>;
|
|
};
|
|
};
|
|
|
|
amba {
|
|
compatible = "arm,amba-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
vica: intc@0x10140000 {
|
|
compatible = "arm,versatile-vic";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x10140000 0x20>;
|
|
};
|
|
|
|
vicb: intc@0x10140020 {
|
|
compatible = "arm,versatile-vic";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x10140020 0x20>;
|
|
};
|
|
|
|
uart0: uart@101fd000 {
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
reg = <0x101fd000 0x1000>;
|
|
interrupt-parent = <&vica>;
|
|
interrupts = <12>;
|
|
clocks = <&uart0clk>, <&pclkuart0>;
|
|
clock-names = "uartclk", "apb_pclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart0_default_mux>;
|
|
};
|
|
|
|
uart1: uart@101fb000 {
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
reg = <0x101fb000 0x1000>;
|
|
interrupt-parent = <&vica>;
|
|
interrupts = <17>;
|
|
clocks = <&uart1clk>, <&pclkuart1>;
|
|
clock-names = "uartclk", "apb_pclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart1_default_mux>;
|
|
};
|
|
|
|
uart2: uart@101f2000 {
|
|
compatible = "arm,pl011", "arm,primecell";
|
|
reg = <0x101f2000 0x1000>;
|
|
interrupt-parent = <&vica>;
|
|
interrupts = <28>;
|
|
clocks = <&uart2clk>, <&pclkuart2>;
|
|
clock-names = "uartclk", "apb_pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
rng: rng@101b0000 {
|
|
compatible = "arm,primecell";
|
|
reg = <0x101b0000 0x1000>;
|
|
clocks = <&rngcclk>, <&hclkrng>;
|
|
clock-names = "rng", "apb_pclk";
|
|
};
|
|
|
|
rtc: rtc@101e8000 {
|
|
compatible = "arm,pl031", "arm,primecell";
|
|
reg = <0x101e8000 0x1000>;
|
|
clocks = <&pclk>;
|
|
clock-names = "apb_pclk";
|
|
interrupt-parent = <&vica>;
|
|
interrupts = <10>;
|
|
};
|
|
|
|
mmcsd: sdi@101f6000 {
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
reg = <0x101f6000 0x1000>;
|
|
clocks = <&sdiclk>, <&pclksdi>;
|
|
clock-names = "mclk", "apb_pclk";
|
|
interrupt-parent = <&vica>;
|
|
interrupts = <22>;
|
|
max-frequency = <48000000>;
|
|
bus-width = <4>;
|
|
mmc-cap-mmc-highspeed;
|
|
mmc-cap-sd-highspeed;
|
|
cd-gpios = <&gpio3 15 0x1>;
|
|
cd-inverted;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>;
|
|
};
|
|
};
|
|
};
|