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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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cbd5b982f6
Not all ColdFire SoC parts that have an MMU also have an FPU - so set an FPU type (via m68k_fputype) appropriate for the configured platform. With this set correctly /proc/cpuinfo will report FPU "none" on devices that don't have one. And kernel code paths that initialize FPU hardware will now only execute if an FPU is actually present. Signed-off-by: Greg Ungerer <gerg@linux-m68k.org>
109 lines
3.4 KiB
C
109 lines
3.4 KiB
C
/*
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* m54xxsim.h -- ColdFire 547x/548x System Integration Unit support.
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*/
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#ifndef m54xxsim_h
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#define m54xxsim_h
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#define CPU_NAME "COLDFIRE(m54xx)"
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#define CPU_INSTR_PER_JIFFY 2
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#define MCF_BUSCLK (MCF_CLK / 2)
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#define MACHINE MACH_M54XX
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#define FPUTYPE FPU_COLDFIRE
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#include <asm/m54xxacr.h>
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#define MCFINT_VECBASE 64
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/*
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* Interrupt Controller Registers
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*/
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#define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */
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#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
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#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
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#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
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#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
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#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
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#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
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#define MCFINTC_IRLR 0x18 /* */
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#define MCFINTC_IACKL 0x19 /* */
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#define MCFINTC_ICR0 0x40 /* Base ICR register */
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/*
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* UART module.
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*/
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#define MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */
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#define MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */
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#define MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */
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#define MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */
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/*
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* Define system peripheral IRQ usage.
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*/
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#define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */
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#define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */
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#define MCF_IRQ_UART0 (MCFINT_VECBASE + 35)
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#define MCF_IRQ_UART1 (MCFINT_VECBASE + 34)
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#define MCF_IRQ_UART2 (MCFINT_VECBASE + 33)
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#define MCF_IRQ_UART3 (MCFINT_VECBASE + 32)
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/*
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* Slice Timer support.
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*/
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#define MCFSLT_TIMER0 (MCF_MBAR + 0x900) /* Base addr TIMER0 */
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#define MCFSLT_TIMER1 (MCF_MBAR + 0x910) /* Base addr TIMER1 */
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/*
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* Generic GPIO support
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*/
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#define MCFGPIO_PODR (MCF_MBAR + 0xA00)
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#define MCFGPIO_PDDR (MCF_MBAR + 0xA10)
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#define MCFGPIO_PPDR (MCF_MBAR + 0xA20)
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#define MCFGPIO_SETR (MCF_MBAR + 0xA20)
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#define MCFGPIO_CLRR (MCF_MBAR + 0xA30)
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#define MCFGPIO_PIN_MAX 136 /* 128 gpio + 8 eport */
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#define MCFGPIO_IRQ_MAX 8
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#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
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/*
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* EDGE Port support.
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*/
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#define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */
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#define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */
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#define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */
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#define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */
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#define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */
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#define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */
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/*
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* Pin Assignment register definitions
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*/
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#define MCFGPIO_PAR_FBCTL (MCF_MBAR + 0xA40)
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#define MCFGPIO_PAR_FBCS (MCF_MBAR + 0xA42)
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#define MCFGPIO_PAR_DMA (MCF_MBAR + 0xA43)
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#define MCFGPIO_PAR_FECI2CIRQ (MCF_MBAR + 0xA44)
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#define MCFGPIO_PAR_PCIBG (MCF_MBAR + 0xA48) /* PCI bus grant */
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#define MCFGPIO_PAR_PCIBR (MCF_MBAR + 0xA4A) /* PCI */
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#define MCFGPIO_PAR_PSC0 (MCF_MBAR + 0xA4F)
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#define MCFGPIO_PAR_PSC1 (MCF_MBAR + 0xA4E)
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#define MCFGPIO_PAR_PSC2 (MCF_MBAR + 0xA4D)
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#define MCFGPIO_PAR_PSC3 (MCF_MBAR + 0xA4C)
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#define MCFGPIO_PAR_DSPI (MCF_MBAR + 0xA50)
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#define MCFGPIO_PAR_TIMER (MCF_MBAR + 0xA52)
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#define MCF_PAR_SDA (0x0008)
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#define MCF_PAR_SCL (0x0004)
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#define MCF_PAR_PSC_TXD (0x04)
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#define MCF_PAR_PSC_RXD (0x08)
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#define MCF_PAR_PSC_CTS_GPIO (0x00)
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#define MCF_PAR_PSC_CTS_BCLK (0x80)
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#define MCF_PAR_PSC_CTS_CTS (0xC0)
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#define MCF_PAR_PSC_RTS_GPIO (0x00)
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#define MCF_PAR_PSC_RTS_FSYNC (0x20)
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#define MCF_PAR_PSC_RTS_RTS (0x30)
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#define MCF_PAR_PSC_CANRX (0x40)
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#endif /* m54xxsim_h */
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