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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 10:37:51 +07:00
81fca03ae7
Set dma_masks for SGIWD93 and SGISEEQ otherwise DMA allocations fails and causes not working SCSI/ethernet. Signed-off-by: Thomas Bogendoerfer <tbogendoerfer@suse.de> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org
224 lines
4.9 KiB
C
224 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/init.h>
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#include <linux/if_ether.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <asm/paccess.h>
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#include <asm/sgi/ip22.h>
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#include <asm/sgi/hpc3.h>
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#include <asm/sgi/mc.h>
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#include <asm/sgi/seeq.h>
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#include <asm/sgi/wd.h>
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static struct resource sgiwd93_0_resources[] = {
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{
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.name = "eth0 irq",
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.start = SGI_WD93_0_IRQ,
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.end = SGI_WD93_0_IRQ,
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.flags = IORESOURCE_IRQ
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}
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};
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static struct sgiwd93_platform_data sgiwd93_0_pd = {
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.unit = 0,
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.irq = SGI_WD93_0_IRQ,
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};
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static u64 sgiwd93_0_dma_mask = DMA_BIT_MASK(32);
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static struct platform_device sgiwd93_0_device = {
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.name = "sgiwd93",
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.id = 0,
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.num_resources = ARRAY_SIZE(sgiwd93_0_resources),
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.resource = sgiwd93_0_resources,
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.dev = {
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.platform_data = &sgiwd93_0_pd,
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.dma_mask = &sgiwd93_0_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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static struct resource sgiwd93_1_resources[] = {
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{
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.name = "eth0 irq",
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.start = SGI_WD93_1_IRQ,
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.end = SGI_WD93_1_IRQ,
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.flags = IORESOURCE_IRQ
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}
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};
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static struct sgiwd93_platform_data sgiwd93_1_pd = {
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.unit = 1,
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.irq = SGI_WD93_1_IRQ,
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};
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static u64 sgiwd93_1_dma_mask = DMA_BIT_MASK(32);
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static struct platform_device sgiwd93_1_device = {
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.name = "sgiwd93",
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.id = 1,
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.num_resources = ARRAY_SIZE(sgiwd93_1_resources),
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.resource = sgiwd93_1_resources,
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.dev = {
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.platform_data = &sgiwd93_1_pd,
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.dma_mask = &sgiwd93_1_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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/*
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* Create a platform device for the GPI port that receives the
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* image data from the embedded camera.
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*/
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static int __init sgiwd93_devinit(void)
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{
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int res;
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sgiwd93_0_pd.hregs = &hpc3c0->scsi_chan0;
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sgiwd93_0_pd.wdregs = (unsigned char *) hpc3c0->scsi0_ext;
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res = platform_device_register(&sgiwd93_0_device);
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if (res)
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return res;
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if (!ip22_is_fullhouse())
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return 0;
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sgiwd93_1_pd.hregs = &hpc3c0->scsi_chan1;
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sgiwd93_1_pd.wdregs = (unsigned char *) hpc3c0->scsi1_ext;
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return platform_device_register(&sgiwd93_1_device);
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}
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device_initcall(sgiwd93_devinit);
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static struct resource sgiseeq_0_resources[] = {
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{
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.name = "eth0 irq",
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.start = SGI_ENET_IRQ,
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.end = SGI_ENET_IRQ,
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.flags = IORESOURCE_IRQ
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}
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};
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static struct sgiseeq_platform_data eth0_pd;
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static u64 sgiseeq_dma_mask = DMA_BIT_MASK(32);
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static struct platform_device eth0_device = {
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.name = "sgiseeq",
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.id = 0,
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.num_resources = ARRAY_SIZE(sgiseeq_0_resources),
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.resource = sgiseeq_0_resources,
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.dev = {
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.platform_data = ð0_pd,
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.dma_mask = &sgiseeq_dma_mask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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};
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static struct resource sgiseeq_1_resources[] = {
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{
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.name = "eth1 irq",
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.start = SGI_GIO_0_IRQ,
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.end = SGI_GIO_0_IRQ,
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.flags = IORESOURCE_IRQ
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}
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};
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static struct sgiseeq_platform_data eth1_pd;
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static struct platform_device eth1_device = {
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.name = "sgiseeq",
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.id = 1,
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.num_resources = ARRAY_SIZE(sgiseeq_1_resources),
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.resource = sgiseeq_1_resources,
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.dev = {
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.platform_data = ð1_pd,
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},
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};
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/*
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* Create a platform device for the GPI port that receives the
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* image data from the embedded camera.
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*/
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static int __init sgiseeq_devinit(void)
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{
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unsigned int pbdma __maybe_unused;
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int res, i;
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eth0_pd.hpc = hpc3c0;
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eth0_pd.irq = SGI_ENET_IRQ;
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#define EADDR_NVOFS 250
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for (i = 0; i < 3; i++) {
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unsigned short tmp = ip22_nvram_read(EADDR_NVOFS / 2 + i);
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eth0_pd.mac[2 * i] = tmp >> 8;
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eth0_pd.mac[2 * i + 1] = tmp & 0xff;
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}
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res = platform_device_register(ð0_device);
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if (res)
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return res;
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/* Second HPC is missing? */
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if (ip22_is_fullhouse() ||
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get_dbe(pbdma, (unsigned int *)&hpc3c1->pbdma[1]))
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return 0;
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sgimc->giopar |= SGIMC_GIOPAR_MASTEREXP1 | SGIMC_GIOPAR_EXP164 |
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SGIMC_GIOPAR_HPC264;
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hpc3c1->pbus_piocfg[0][0] = 0x3ffff;
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/* interrupt/config register on Challenge S Mezz board */
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hpc3c1->pbus_extregs[0][0] = 0x30;
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eth1_pd.hpc = hpc3c1;
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eth1_pd.irq = SGI_GIO_0_IRQ;
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#define EADDR_NVOFS 250
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for (i = 0; i < 3; i++) {
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unsigned short tmp = ip22_eeprom_read(&hpc3c1->eeprom,
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EADDR_NVOFS / 2 + i);
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eth1_pd.mac[2 * i] = tmp >> 8;
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eth1_pd.mac[2 * i + 1] = tmp & 0xff;
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}
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return platform_device_register(ð1_device);
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}
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device_initcall(sgiseeq_devinit);
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static int __init sgi_hal2_devinit(void)
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{
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return IS_ERR(platform_device_register_simple("sgihal2", 0, NULL, 0));
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}
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device_initcall(sgi_hal2_devinit);
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static int __init sgi_button_devinit(void)
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{
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if (ip22_is_fullhouse())
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return 0; /* full house has no volume buttons */
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return IS_ERR(platform_device_register_simple("sgibtns", -1, NULL, 0));
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}
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device_initcall(sgi_button_devinit);
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static int __init sgi_ds1286_devinit(void)
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{
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struct resource res;
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memset(&res, 0, sizeof(res));
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res.start = HPC3_CHIP0_BASE + offsetof(struct hpc3_regs, rtcregs);
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res.end = res.start + sizeof(hpc3c0->rtcregs) - 1;
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res.flags = IORESOURCE_MEM;
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return IS_ERR(platform_device_register_simple("rtc-ds1286", -1,
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&res, 1));
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}
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device_initcall(sgi_ds1286_devinit);
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