mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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fcdc653751
RISC-V has the concept of a cpu level interrupt controller. The interface for it is split between a standardized part that is exposed as bits in the mstatus/sstatus register and the mie/mip/sie/sip CRS. But the bit to actually trigger IPIs is not standardized and just mentioned as implementable using MMIO. Add support for IPIs using MMIO using the SiFive clint layout (which is also shared by Ariane, Kendryte and the Qemu virt platform). Additionally the MMIO block also supports the time value and timer compare registers, so they are also set up using the same OF node. Support for other layouts should also be relatively easy to add in the future. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Anup Patel <anup@brainfault.org> [paul.walmsley@sifive.com: update include guard format; fix checkpatch issues; minor commit message cleanup] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
87 lines
1.9 KiB
C
87 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
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* Chen Liqin <liqin.chen@sunplusct.com>
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* Lennox Wu <lennox.wu@sunplusct.com>
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* Copyright (C) 2012 Regents of the University of California
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*/
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/memblock.h>
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#include <linux/sched.h>
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#include <linux/console.h>
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#include <linux/screen_info.h>
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#include <linux/of_fdt.h>
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#include <linux/of_platform.h>
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#include <linux/sched/task.h>
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#include <linux/swiotlb.h>
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#include <asm/clint.h>
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#include <asm/setup.h>
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#include <asm/sections.h>
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#include <asm/pgtable.h>
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#include <asm/smp.h>
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#include <asm/tlbflush.h>
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#include <asm/thread_info.h>
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#include "head.h"
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#ifdef CONFIG_DUMMY_CONSOLE
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struct screen_info screen_info = {
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.orig_video_lines = 30,
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.orig_video_cols = 80,
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.orig_video_mode = 0,
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.orig_video_ega_bx = 0,
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.orig_video_isVGA = 1,
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.orig_video_points = 8
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};
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#endif
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/* The lucky hart to first increment this variable will boot the other cores */
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atomic_t hart_lottery;
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unsigned long boot_cpu_hartid;
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void __init parse_dtb(void)
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{
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if (early_init_dt_scan(dtb_early_va))
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return;
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pr_err("No DTB passed to the kernel\n");
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#ifdef CONFIG_CMDLINE_FORCE
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strlcpy(boot_command_line, CONFIG_CMDLINE, COMMAND_LINE_SIZE);
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pr_info("Forcing kernel command line to: %s\n", boot_command_line);
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#endif
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}
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void __init setup_arch(char **cmdline_p)
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{
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init_mm.start_code = (unsigned long) _stext;
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init_mm.end_code = (unsigned long) _etext;
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init_mm.end_data = (unsigned long) _edata;
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init_mm.brk = (unsigned long) _end;
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*cmdline_p = boot_command_line;
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parse_early_param();
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setup_bootmem();
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paging_init();
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unflatten_device_tree();
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clint_init_boot_cpu();
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#ifdef CONFIG_SWIOTLB
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swiotlb_init(1);
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#endif
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#ifdef CONFIG_SMP
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setup_smp();
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#endif
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#ifdef CONFIG_DUMMY_CONSOLE
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conswitchp = &dummy_con;
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#endif
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riscv_fill_hwcap();
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}
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