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42a3b4f25a
Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
599 lines
18 KiB
C
599 lines
18 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Inline assembly cache operations.
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*
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* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
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* Copyright (C) 1997 - 2002 Ralf Baechle (ralf@gnu.org)
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* Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org)
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*/
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#ifndef _ASM_R4KCACHE_H
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#define _ASM_R4KCACHE_H
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#include <asm/asm.h>
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#include <asm/cacheops.h>
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/*
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* This macro return a properly sign-extended address suitable as base address
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* for indexed cache operations. Two issues here:
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*
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* - The MIPS32 and MIPS64 specs permit an implementation to directly derive
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* the index bits from the virtual address. This breaks with tradition
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* set by the R4000. To keep unpleassant surprises from happening we pick
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* an address in KSEG0 / CKSEG0.
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* - We need a properly sign extended address for 64-bit code. To get away
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* without ifdefs we let the compiler do it by a type cast.
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*/
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#define INDEX_BASE CKSEG0
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#define cache_op(op,addr) \
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__asm__ __volatile__( \
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" .set noreorder \n" \
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" .set mips3\n\t \n" \
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" cache %0, %1 \n" \
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" .set mips0 \n" \
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" .set reorder" \
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: \
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: "i" (op), "m" (*(unsigned char *)(addr)))
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static inline void flush_icache_line_indexed(unsigned long addr)
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{
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cache_op(Index_Invalidate_I, addr);
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}
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static inline void flush_dcache_line_indexed(unsigned long addr)
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{
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cache_op(Index_Writeback_Inv_D, addr);
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}
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static inline void flush_scache_line_indexed(unsigned long addr)
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{
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cache_op(Index_Writeback_Inv_SD, addr);
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}
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static inline void flush_icache_line(unsigned long addr)
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{
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cache_op(Hit_Invalidate_I, addr);
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}
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static inline void flush_dcache_line(unsigned long addr)
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{
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cache_op(Hit_Writeback_Inv_D, addr);
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}
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static inline void invalidate_dcache_line(unsigned long addr)
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{
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cache_op(Hit_Invalidate_D, addr);
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}
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static inline void invalidate_scache_line(unsigned long addr)
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{
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cache_op(Hit_Invalidate_SD, addr);
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}
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static inline void flush_scache_line(unsigned long addr)
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{
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cache_op(Hit_Writeback_Inv_SD, addr);
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}
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/*
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* The next two are for badland addresses like signal trampolines.
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*/
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static inline void protected_flush_icache_line(unsigned long addr)
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{
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__asm__ __volatile__(
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".set noreorder\n\t"
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".set mips3\n"
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"1:\tcache %0,(%1)\n"
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"2:\t.set mips0\n\t"
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".set reorder\n\t"
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".section\t__ex_table,\"a\"\n\t"
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STR(PTR)"\t1b,2b\n\t"
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".previous"
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:
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: "i" (Hit_Invalidate_I), "r" (addr));
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}
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/*
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* R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D
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* cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style
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* caches. We're talking about one cacheline unnecessarily getting invalidated
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* here so the penaltiy isn't overly hard.
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*/
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static inline void protected_writeback_dcache_line(unsigned long addr)
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{
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__asm__ __volatile__(
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".set noreorder\n\t"
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".set mips3\n"
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"1:\tcache %0,(%1)\n"
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"2:\t.set mips0\n\t"
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".set reorder\n\t"
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".section\t__ex_table,\"a\"\n\t"
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STR(PTR)"\t1b,2b\n\t"
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".previous"
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:
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: "i" (Hit_Writeback_Inv_D), "r" (addr));
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}
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static inline void protected_writeback_scache_line(unsigned long addr)
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{
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__asm__ __volatile__(
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".set noreorder\n\t"
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".set mips3\n"
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"1:\tcache %0,(%1)\n"
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"2:\t.set mips0\n\t"
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".set reorder\n\t"
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".section\t__ex_table,\"a\"\n\t"
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STR(PTR)"\t1b,2b\n\t"
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".previous"
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:
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: "i" (Hit_Writeback_Inv_SD), "r" (addr));
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}
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/*
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* This one is RM7000-specific
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*/
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static inline void invalidate_tcache_page(unsigned long addr)
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{
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cache_op(Page_Invalidate_T, addr);
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}
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#define cache16_unroll32(base,op) \
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__asm__ __volatile__( \
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" .set noreorder \n" \
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" .set mips3 \n" \
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" cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \
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" cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \
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" cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \
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" cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \
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" cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \
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" cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \
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" cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \
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" cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \
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" cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \
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" cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \
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" cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \
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" cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \
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" cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \
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" cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \
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" cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \
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" cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \
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" .set mips0 \n" \
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" .set reorder \n" \
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: \
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: "r" (base), \
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"i" (op));
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static inline void blast_dcache16(void)
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{
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unsigned long start = INDEX_BASE;
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unsigned long end = start + current_cpu_data.dcache.waysize;
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unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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unsigned long ws_end = current_cpu_data.dcache.ways <<
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current_cpu_data.dcache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x200)
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cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
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}
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static inline void blast_dcache16_page(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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do {
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cache16_unroll32(start,Hit_Writeback_Inv_D);
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start += 0x200;
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} while (start < end);
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}
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static inline void blast_dcache16_page_indexed(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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unsigned long ws_end = current_cpu_data.dcache.ways <<
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current_cpu_data.dcache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x200)
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cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
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}
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static inline void blast_icache16(void)
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{
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unsigned long start = INDEX_BASE;
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unsigned long end = start + current_cpu_data.icache.waysize;
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unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
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unsigned long ws_end = current_cpu_data.icache.ways <<
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current_cpu_data.icache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x200)
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cache16_unroll32(addr|ws,Index_Invalidate_I);
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}
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static inline void blast_icache16_page(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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do {
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cache16_unroll32(start,Hit_Invalidate_I);
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start += 0x200;
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} while (start < end);
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}
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static inline void blast_icache16_page_indexed(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
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unsigned long ws_end = current_cpu_data.icache.ways <<
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current_cpu_data.icache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x200)
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cache16_unroll32(addr|ws,Index_Invalidate_I);
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}
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static inline void blast_scache16(void)
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{
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unsigned long start = INDEX_BASE;
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unsigned long end = start + current_cpu_data.scache.waysize;
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unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
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unsigned long ws_end = current_cpu_data.scache.ways <<
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current_cpu_data.scache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x200)
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cache16_unroll32(addr|ws,Index_Writeback_Inv_SD);
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}
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static inline void blast_scache16_page(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = page + PAGE_SIZE;
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do {
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cache16_unroll32(start,Hit_Writeback_Inv_SD);
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start += 0x200;
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} while (start < end);
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}
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static inline void blast_scache16_page_indexed(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
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unsigned long ws_end = current_cpu_data.scache.ways <<
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current_cpu_data.scache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x200)
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cache16_unroll32(addr|ws,Index_Writeback_Inv_SD);
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}
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#define cache32_unroll32(base,op) \
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__asm__ __volatile__( \
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" .set noreorder \n" \
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" .set mips3 \n" \
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" cache %1, 0x000(%0); cache %1, 0x020(%0) \n" \
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" cache %1, 0x040(%0); cache %1, 0x060(%0) \n" \
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" cache %1, 0x080(%0); cache %1, 0x0a0(%0) \n" \
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" cache %1, 0x0c0(%0); cache %1, 0x0e0(%0) \n" \
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" cache %1, 0x100(%0); cache %1, 0x120(%0) \n" \
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" cache %1, 0x140(%0); cache %1, 0x160(%0) \n" \
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" cache %1, 0x180(%0); cache %1, 0x1a0(%0) \n" \
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" cache %1, 0x1c0(%0); cache %1, 0x1e0(%0) \n" \
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" cache %1, 0x200(%0); cache %1, 0x220(%0) \n" \
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" cache %1, 0x240(%0); cache %1, 0x260(%0) \n" \
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" cache %1, 0x280(%0); cache %1, 0x2a0(%0) \n" \
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" cache %1, 0x2c0(%0); cache %1, 0x2e0(%0) \n" \
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" cache %1, 0x300(%0); cache %1, 0x320(%0) \n" \
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" cache %1, 0x340(%0); cache %1, 0x360(%0) \n" \
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" cache %1, 0x380(%0); cache %1, 0x3a0(%0) \n" \
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" cache %1, 0x3c0(%0); cache %1, 0x3e0(%0) \n" \
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" .set mips0 \n" \
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" .set reorder \n" \
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: \
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: "r" (base), \
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"i" (op));
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static inline void blast_dcache32(void)
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{
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unsigned long start = INDEX_BASE;
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unsigned long end = start + current_cpu_data.dcache.waysize;
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unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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unsigned long ws_end = current_cpu_data.dcache.ways <<
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current_cpu_data.dcache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x400)
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cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
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}
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static inline void blast_dcache32_page(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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do {
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cache32_unroll32(start,Hit_Writeback_Inv_D);
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start += 0x400;
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} while (start < end);
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}
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static inline void blast_dcache32_page_indexed(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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unsigned long ws_end = current_cpu_data.dcache.ways <<
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current_cpu_data.dcache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x400)
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cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
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}
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static inline void blast_icache32(void)
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{
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unsigned long start = INDEX_BASE;
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unsigned long end = start + current_cpu_data.icache.waysize;
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unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
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unsigned long ws_end = current_cpu_data.icache.ways <<
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current_cpu_data.icache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x400)
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cache32_unroll32(addr|ws,Index_Invalidate_I);
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}
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static inline void blast_icache32_page(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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do {
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cache32_unroll32(start,Hit_Invalidate_I);
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start += 0x400;
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} while (start < end);
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}
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static inline void blast_icache32_page_indexed(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
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unsigned long ws_end = current_cpu_data.icache.ways <<
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current_cpu_data.icache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x400)
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cache32_unroll32(addr|ws,Index_Invalidate_I);
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}
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static inline void blast_scache32(void)
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{
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unsigned long start = INDEX_BASE;
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unsigned long end = start + current_cpu_data.scache.waysize;
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unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
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unsigned long ws_end = current_cpu_data.scache.ways <<
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current_cpu_data.scache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x400)
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cache32_unroll32(addr|ws,Index_Writeback_Inv_SD);
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}
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static inline void blast_scache32_page(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = page + PAGE_SIZE;
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do {
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cache32_unroll32(start,Hit_Writeback_Inv_SD);
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start += 0x400;
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} while (start < end);
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}
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static inline void blast_scache32_page_indexed(unsigned long page)
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{
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
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unsigned long ws_end = current_cpu_data.scache.ways <<
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current_cpu_data.scache.waybit;
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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for (addr = start; addr < end; addr += 0x400)
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cache32_unroll32(addr|ws,Index_Writeback_Inv_SD);
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}
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#define cache64_unroll32(base,op) \
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__asm__ __volatile__( \
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" .set noreorder \n" \
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" .set mips3 \n" \
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" cache %1, 0x000(%0); cache %1, 0x040(%0) \n" \
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" cache %1, 0x080(%0); cache %1, 0x0c0(%0) \n" \
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" cache %1, 0x100(%0); cache %1, 0x140(%0) \n" \
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" cache %1, 0x180(%0); cache %1, 0x1c0(%0) \n" \
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" cache %1, 0x200(%0); cache %1, 0x240(%0) \n" \
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" cache %1, 0x280(%0); cache %1, 0x2c0(%0) \n" \
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" cache %1, 0x300(%0); cache %1, 0x340(%0) \n" \
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" cache %1, 0x380(%0); cache %1, 0x3c0(%0) \n" \
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" cache %1, 0x400(%0); cache %1, 0x440(%0) \n" \
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" cache %1, 0x480(%0); cache %1, 0x4c0(%0) \n" \
|
|
" cache %1, 0x500(%0); cache %1, 0x540(%0) \n" \
|
|
" cache %1, 0x580(%0); cache %1, 0x5c0(%0) \n" \
|
|
" cache %1, 0x600(%0); cache %1, 0x640(%0) \n" \
|
|
" cache %1, 0x680(%0); cache %1, 0x6c0(%0) \n" \
|
|
" cache %1, 0x700(%0); cache %1, 0x740(%0) \n" \
|
|
" cache %1, 0x780(%0); cache %1, 0x7c0(%0) \n" \
|
|
" .set mips0 \n" \
|
|
" .set reorder \n" \
|
|
: \
|
|
: "r" (base), \
|
|
"i" (op));
|
|
|
|
static inline void blast_icache64(void)
|
|
{
|
|
unsigned long start = INDEX_BASE;
|
|
unsigned long end = start + current_cpu_data.icache.waysize;
|
|
unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
|
|
unsigned long ws_end = current_cpu_data.icache.ways <<
|
|
current_cpu_data.icache.waybit;
|
|
unsigned long ws, addr;
|
|
|
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
|
for (addr = start; addr < end; addr += 0x800)
|
|
cache64_unroll32(addr|ws,Index_Invalidate_I);
|
|
}
|
|
|
|
static inline void blast_icache64_page(unsigned long page)
|
|
{
|
|
unsigned long start = page;
|
|
unsigned long end = start + PAGE_SIZE;
|
|
|
|
do {
|
|
cache64_unroll32(start,Hit_Invalidate_I);
|
|
start += 0x800;
|
|
} while (start < end);
|
|
}
|
|
|
|
static inline void blast_icache64_page_indexed(unsigned long page)
|
|
{
|
|
unsigned long start = page;
|
|
unsigned long end = start + PAGE_SIZE;
|
|
unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
|
|
unsigned long ws_end = current_cpu_data.icache.ways <<
|
|
current_cpu_data.icache.waybit;
|
|
unsigned long ws, addr;
|
|
|
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
|
for (addr = start; addr < end; addr += 0x800)
|
|
cache64_unroll32(addr|ws,Index_Invalidate_I);
|
|
}
|
|
|
|
static inline void blast_scache64(void)
|
|
{
|
|
unsigned long start = INDEX_BASE;
|
|
unsigned long end = start + current_cpu_data.scache.waysize;
|
|
unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
|
|
unsigned long ws_end = current_cpu_data.scache.ways <<
|
|
current_cpu_data.scache.waybit;
|
|
unsigned long ws, addr;
|
|
|
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
|
for (addr = start; addr < end; addr += 0x800)
|
|
cache64_unroll32(addr|ws,Index_Writeback_Inv_SD);
|
|
}
|
|
|
|
static inline void blast_scache64_page(unsigned long page)
|
|
{
|
|
unsigned long start = page;
|
|
unsigned long end = page + PAGE_SIZE;
|
|
|
|
do {
|
|
cache64_unroll32(start,Hit_Writeback_Inv_SD);
|
|
start += 0x800;
|
|
} while (start < end);
|
|
}
|
|
|
|
static inline void blast_scache64_page_indexed(unsigned long page)
|
|
{
|
|
unsigned long start = page;
|
|
unsigned long end = start + PAGE_SIZE;
|
|
unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
|
|
unsigned long ws_end = current_cpu_data.scache.ways <<
|
|
current_cpu_data.scache.waybit;
|
|
unsigned long ws, addr;
|
|
|
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
|
for (addr = start; addr < end; addr += 0x800)
|
|
cache64_unroll32(addr|ws,Index_Writeback_Inv_SD);
|
|
}
|
|
|
|
#define cache128_unroll32(base,op) \
|
|
__asm__ __volatile__( \
|
|
" .set noreorder \n" \
|
|
" .set mips3 \n" \
|
|
" cache %1, 0x000(%0); cache %1, 0x080(%0) \n" \
|
|
" cache %1, 0x100(%0); cache %1, 0x180(%0) \n" \
|
|
" cache %1, 0x200(%0); cache %1, 0x280(%0) \n" \
|
|
" cache %1, 0x300(%0); cache %1, 0x380(%0) \n" \
|
|
" cache %1, 0x400(%0); cache %1, 0x480(%0) \n" \
|
|
" cache %1, 0x500(%0); cache %1, 0x580(%0) \n" \
|
|
" cache %1, 0x600(%0); cache %1, 0x680(%0) \n" \
|
|
" cache %1, 0x700(%0); cache %1, 0x780(%0) \n" \
|
|
" cache %1, 0x800(%0); cache %1, 0x880(%0) \n" \
|
|
" cache %1, 0x900(%0); cache %1, 0x980(%0) \n" \
|
|
" cache %1, 0xa00(%0); cache %1, 0xa80(%0) \n" \
|
|
" cache %1, 0xb00(%0); cache %1, 0xb80(%0) \n" \
|
|
" cache %1, 0xc00(%0); cache %1, 0xc80(%0) \n" \
|
|
" cache %1, 0xd00(%0); cache %1, 0xd80(%0) \n" \
|
|
" cache %1, 0xe00(%0); cache %1, 0xe80(%0) \n" \
|
|
" cache %1, 0xf00(%0); cache %1, 0xf80(%0) \n" \
|
|
" .set mips0 \n" \
|
|
" .set reorder \n" \
|
|
: \
|
|
: "r" (base), \
|
|
"i" (op));
|
|
|
|
static inline void blast_scache128(void)
|
|
{
|
|
unsigned long start = INDEX_BASE;
|
|
unsigned long end = start + current_cpu_data.scache.waysize;
|
|
unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
|
|
unsigned long ws_end = current_cpu_data.scache.ways <<
|
|
current_cpu_data.scache.waybit;
|
|
unsigned long ws, addr;
|
|
|
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
|
for (addr = start; addr < end; addr += 0x1000)
|
|
cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
|
|
}
|
|
|
|
static inline void blast_scache128_page(unsigned long page)
|
|
{
|
|
unsigned long start = page;
|
|
unsigned long end = page + PAGE_SIZE;
|
|
|
|
do {
|
|
cache128_unroll32(start,Hit_Writeback_Inv_SD);
|
|
start += 0x1000;
|
|
} while (start < end);
|
|
}
|
|
|
|
static inline void blast_scache128_page_indexed(unsigned long page)
|
|
{
|
|
unsigned long start = page;
|
|
unsigned long end = start + PAGE_SIZE;
|
|
unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
|
|
unsigned long ws_end = current_cpu_data.scache.ways <<
|
|
current_cpu_data.scache.waybit;
|
|
unsigned long ws, addr;
|
|
|
|
for (ws = 0; ws < ws_end; ws += ws_inc)
|
|
for (addr = start; addr < end; addr += 0x1000)
|
|
cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
|
|
}
|
|
|
|
#endif /* _ASM_R4KCACHE_H */
|