mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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3dac219615
This used to be done in .map_io which is supposed to only setup the memory mapping. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
354 lines
8.0 KiB
C
354 lines
8.0 KiB
C
/*
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/map.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/physmap.h>
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#include <linux/i2c.h>
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#include <linux/irq.h>
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#include <mach/common.h>
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#include <mach/hardware.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <asm/mach/map.h>
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#include <mach/gpio.h>
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#include <mach/iomux-mx27.h>
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#include <mach/mxc_nand.h>
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#include "devices-imx27.h"
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/*
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* Base address of PBC controller, CS4
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*/
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#define PBC_BASE_ADDRESS 0xf4300000
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#define PBC_REG_ADDR(offset) (void __force __iomem *) \
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(PBC_BASE_ADDRESS + (offset))
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/* When the PBC address connection is fixed in h/w, defined as 1 */
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#define PBC_ADDR_SH 0
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/* Offsets for the PBC Controller register */
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/*
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* PBC Board version register offset
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*/
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#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
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/*
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* PBC Board control register 1 set address.
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*/
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#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
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/*
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* PBC Board control register 1 clear address.
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*/
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#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
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/* PBC Board Control Register 1 bit definitions */
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#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
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/* to determine the correct external crystal reference */
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#define CKIH_27MHZ_BIT_SET (1 << 3)
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static const int mx27ads_pins[] __initconst = {
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/* UART0 */
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PE12_PF_UART1_TXD,
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PE13_PF_UART1_RXD,
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PE14_PF_UART1_CTS,
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PE15_PF_UART1_RTS,
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/* UART1 */
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PE3_PF_UART2_CTS,
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PE4_PF_UART2_RTS,
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PE6_PF_UART2_TXD,
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PE7_PF_UART2_RXD,
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/* UART2 */
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PE8_PF_UART3_TXD,
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PE9_PF_UART3_RXD,
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PE10_PF_UART3_CTS,
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PE11_PF_UART3_RTS,
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/* UART3 */
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PB26_AF_UART4_RTS,
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PB28_AF_UART4_TXD,
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PB29_AF_UART4_CTS,
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PB31_AF_UART4_RXD,
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/* UART4 */
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PB18_AF_UART5_TXD,
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PB19_AF_UART5_RXD,
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PB20_AF_UART5_CTS,
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PB21_AF_UART5_RTS,
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/* UART5 */
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PB10_AF_UART6_TXD,
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PB12_AF_UART6_CTS,
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PB11_AF_UART6_RXD,
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PB13_AF_UART6_RTS,
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/* FEC */
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PD0_AIN_FEC_TXD0,
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PD1_AIN_FEC_TXD1,
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PD2_AIN_FEC_TXD2,
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PD3_AIN_FEC_TXD3,
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PD4_AOUT_FEC_RX_ER,
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PD5_AOUT_FEC_RXD1,
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PD6_AOUT_FEC_RXD2,
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PD7_AOUT_FEC_RXD3,
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PD8_AF_FEC_MDIO,
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PD9_AIN_FEC_MDC,
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PD10_AOUT_FEC_CRS,
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PD11_AOUT_FEC_TX_CLK,
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PD12_AOUT_FEC_RXD0,
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PD13_AOUT_FEC_RX_DV,
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PD14_AOUT_FEC_RX_CLK,
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PD15_AOUT_FEC_COL,
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PD16_AIN_FEC_TX_ER,
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PF23_AIN_FEC_TX_EN,
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/* I2C2 */
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PC5_PF_I2C2_SDA,
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PC6_PF_I2C2_SCL,
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/* FB */
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PA5_PF_LSCLK,
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PA6_PF_LD0,
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PA7_PF_LD1,
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PA8_PF_LD2,
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PA9_PF_LD3,
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PA10_PF_LD4,
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PA11_PF_LD5,
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PA12_PF_LD6,
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PA13_PF_LD7,
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PA14_PF_LD8,
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PA15_PF_LD9,
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PA16_PF_LD10,
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PA17_PF_LD11,
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PA18_PF_LD12,
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PA19_PF_LD13,
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PA20_PF_LD14,
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PA21_PF_LD15,
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PA22_PF_LD16,
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PA23_PF_LD17,
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PA24_PF_REV,
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PA25_PF_CLS,
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PA26_PF_PS,
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PA27_PF_SPL_SPR,
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PA28_PF_HSYNC,
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PA29_PF_VSYNC,
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PA30_PF_CONTRAST,
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PA31_PF_OE_ACD,
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/* OWIRE */
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PE16_AF_OWIRE,
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/* SDHC1*/
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PE18_PF_SD1_D0,
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PE19_PF_SD1_D1,
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PE20_PF_SD1_D2,
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PE21_PF_SD1_D3,
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PE22_PF_SD1_CMD,
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PE23_PF_SD1_CLK,
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/* SDHC2*/
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PB4_PF_SD2_D0,
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PB5_PF_SD2_D1,
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PB6_PF_SD2_D2,
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PB7_PF_SD2_D3,
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PB8_PF_SD2_CMD,
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PB9_PF_SD2_CLK,
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};
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static const struct mxc_nand_platform_data
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mx27ads_nand_board_info __initconst = {
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.width = 1,
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.hw_ecc = 1,
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};
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/* ADS's NOR flash */
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static struct physmap_flash_data mx27ads_flash_data = {
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.width = 2,
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};
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static struct resource mx27ads_flash_resource = {
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.start = 0xc0000000,
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.end = 0xc0000000 + 0x02000000 - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device mx27ads_nor_mtd_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &mx27ads_flash_data,
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},
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.num_resources = 1,
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.resource = &mx27ads_flash_resource,
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};
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static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = {
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.bitrate = 100000,
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};
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static struct i2c_board_info mx27ads_i2c_devices[] = {
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};
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void lcd_power(int on)
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{
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if (on)
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__raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_SET_REG);
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else
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__raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
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}
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static struct imx_fb_videomode mx27ads_modes[] = {
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{
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.mode = {
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.name = "Sharp-LQ035Q7",
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.refresh = 60,
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.xres = 240,
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.yres = 320,
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.pixclock = 188679, /* in ps (5.3MHz) */
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.hsync_len = 1,
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.left_margin = 9,
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.right_margin = 16,
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.vsync_len = 1,
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.upper_margin = 7,
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.lower_margin = 9,
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},
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.bpp = 16,
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.pcr = 0xFB008BC0,
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},
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};
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static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
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.mode = mx27ads_modes,
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.num_modes = ARRAY_SIZE(mx27ads_modes),
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/*
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* - HSYNC active high
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* - VSYNC active high
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* - clk notenabled while idle
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* - clock inverted
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* - data not inverted
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* - data enable low active
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* - enable sharp mode
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*/
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.pwmr = 0x00A903FF,
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.lscr1 = 0x00120300,
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.dmacr = 0x00020010,
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.lcd_power = lcd_power,
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};
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static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
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void *data)
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{
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return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING,
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"sdhc1-card-detect", data);
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}
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static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
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void *data)
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{
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return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING,
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"sdhc2-card-detect", data);
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}
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static void mx27ads_sdhc1_exit(struct device *dev, void *data)
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{
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free_irq(IRQ_GPIOE(21), data);
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}
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static void mx27ads_sdhc2_exit(struct device *dev, void *data)
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{
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free_irq(IRQ_GPIOB(7), data);
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}
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static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
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.init = mx27ads_sdhc1_init,
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.exit = mx27ads_sdhc1_exit,
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};
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static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
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.init = mx27ads_sdhc2_init,
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.exit = mx27ads_sdhc2_exit,
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};
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static struct platform_device *platform_devices[] __initdata = {
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&mx27ads_nor_mtd_device,
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};
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static const struct imxuart_platform_data uart_pdata __initconst = {
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.flags = IMXUART_HAVE_RTSCTS,
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};
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static void __init mx27ads_board_init(void)
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{
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mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
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"mx27ads");
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imx27_add_imx_uart0(&uart_pdata);
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imx27_add_imx_uart1(&uart_pdata);
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imx27_add_imx_uart2(&uart_pdata);
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imx27_add_imx_uart3(&uart_pdata);
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imx27_add_imx_uart4(&uart_pdata);
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imx27_add_imx_uart5(&uart_pdata);
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imx27_add_mxc_nand(&mx27ads_nand_board_info);
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/* only the i2c master 1 is used on this CPU card */
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i2c_register_board_info(1, mx27ads_i2c_devices,
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ARRAY_SIZE(mx27ads_i2c_devices));
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imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
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imx27_add_imx_fb(&mx27ads_fb_data);
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imx27_add_mxc_mmc(0, &sdhc1_pdata);
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imx27_add_mxc_mmc(1, &sdhc2_pdata);
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imx27_add_fec(NULL);
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platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
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imx27_add_mxc_w1(NULL);
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}
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static void __init mx27ads_timer_init(void)
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{
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unsigned long fref = 26000000;
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if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
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fref = 27000000;
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mx27_clocks_init(fref);
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}
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static struct sys_timer mx27ads_timer = {
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.init = mx27ads_timer_init,
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};
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static struct map_desc mx27ads_io_desc[] __initdata = {
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{
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.virtual = PBC_BASE_ADDRESS,
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.pfn = __phys_to_pfn(MX27_CS4_BASE_ADDR),
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.length = SZ_1M,
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.type = MT_DEVICE,
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},
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};
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static void __init mx27ads_map_io(void)
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{
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mx27_map_io();
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iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
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}
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MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
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/* maintainer: Freescale Semiconductor, Inc. */
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.boot_params = MX27_PHYS_OFFSET + 0x100,
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.map_io = mx27ads_map_io,
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.init_early = imx27_init_early,
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.init_irq = mx27_init_irq,
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.timer = &mx27ads_timer,
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.init_machine = mx27ads_board_init,
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MACHINE_END
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