Tony Lindgren cafeb002cf clk: ti: Implement FAPLL set_rate for the synthesizer ... We can pretty much get any rate out of the FAPLL because of the fractional divider. Let's first try just adjusting the post divider, and if that is not enough, then reprogram both the fractional divider and the post divider. Let's also add a define for the fixed SYNTH_PHASE_K instead of using 8. Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>		2015-03-24 20:26:05 +02:00
..
at91	The clock framework changes for 3.20 contain the usual driver additions,	2015-02-21 12:30:30 -08:00
bcm	clk: Add rate constraints to clocks	2015-02-02 14:23:42 -08:00
berlin	clk: berlin: bg2q: remove non-exist "smemc" gate clock	2015-01-13 10:58:43 -08:00
hisilicon	clk: Add rate constraints to clocks	2015-02-02 14:23:42 -08:00
keystone
mmp	clk: Add rate constraints to clocks	2015-02-02 14:23:42 -08:00
mvebu
mxs	Revert "clk: mxs: Fix invalid 32-bit access to frac registers"	2015-02-18 10:13:26 -08:00
pxa	clk: Replace explicit clk assignment with __clk_hw_set_clk	2015-02-18 09:40:11 -08:00
qcom	clk: Add rate constraints to clocks	2015-02-02 14:23:42 -08:00
rockchip	The clock framework changes for 3.20 contain the usual driver additions,	2015-02-21 12:30:30 -08:00
samsung	The clock framework changes for 3.20 contain the usual driver additions,	2015-02-21 12:30:30 -08:00
shmobile	The clock framework changes for 3.20 contain the usual driver additions,	2015-02-21 12:30:30 -08:00
sirf
socfpga
spear
st	clk: Replace explicit clk assignment with __clk_hw_set_clk	2015-02-18 09:40:11 -08:00
sunxi	The clock framework changes for 3.20 contain the usual driver additions,	2015-02-21 12:30:30 -08:00
tegra	clk: Replace explicit clk assignment with __clk_hw_set_clk	2015-02-18 09:40:11 -08:00
ti	clk: ti: Implement FAPLL set_rate for the synthesizer	2015-03-24 20:26:05 +02:00
ux500	clk: ux500: Drop use of clk-private.h	2015-01-27 11:56:33 -08:00
versatile
x86
zynq	clk: zynq: Force CPU_2X clock to be ungated	2015-01-27 17:00:24 -08:00
clk-asm9260.c	ARM: clk: add clk-asm9260 driver	2015-01-20 10:10:51 -08:00
clk-axi-clkgen.c
clk-axm5516.c
clk-bcm2835.c
clk-cdce706.c	clk: TI CDCE706 clock synthesizer driver	2015-01-17 13:52:40 -08:00
clk-clps711x.c
clk-composite.c	clk: Replace explicit clk assignment with __clk_hw_set_clk	2015-02-18 09:40:11 -08:00
clk-conf.c
clk-devres.c
clk-divider.c	clk: divider: Make generic for usage elsewhere	2015-01-27 11:48:52 -08:00
clk-efm32gg.c
clk-fixed-factor.c
clk-fixed-rate.c
clk-fractional-divider.c
clk-gate.c	clk-gate: fix bit # check in clk_register_gate()	2015-01-20 10:09:05 -08:00
clk-gpio-gate.c
clk-highbank.c
clk-ls1x.c
clk-max77686.c
clk-max77802.c
clk-max-gen.c
clk-max-gen.h
clk-moxart.c
clk-mux.c	clk: Add clk_unregister_{divider, gate, mux} to close memory leak	2015-01-17 13:52:41 -08:00
clk-nomadik.c
clk-nspire.c
clk-palmas.c
clk-qoriq.c	clk: qoriq: Add support for the platform PLL	2015-02-18 09:56:43 -08:00
clk-rk808.c
clk-s2mps11.c
clk-si570.c
clk-si5351.c
clk-si5351.h
clk-twl6040.c
clk-u300.c
clk-vt8500.c
clk-wm831x.c
clk-xgene.c
clk.c	The clock framework changes for 3.20 contain the usual driver additions,	2015-02-21 12:30:30 -08:00
clk.h	clkdev: Always allocate a struct clk and call __clk_get() w/ CCF	2015-02-06 17:53:20 -08:00
clkdev.c	clkdev: Always allocate a struct clk and call __clk_get() w/ CCF	2015-02-06 17:53:20 -08:00
Kconfig	The clock framework changes for 3.20 contain the usual driver additions,	2015-02-21 12:30:30 -08:00
Makefile	ARM: clk: add clk-asm9260 driver	2015-01-20 10:10:51 -08:00