mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 16:26:43 +07:00
945005409b
Fix up inconsistent usage of upper and lowercase letters in "Samsung" and "Exynos" names. "SAMSUNG" and "EXYNOS" are not abbreviations but regular trademarked names. Therefore they should be written with lowercase letters starting with capital letter. The lowercase "Exynos" name is promoted by its manufacturer Samsung Electronics Co., Ltd., in advertisement materials and on website. Although advertisement materials usually use uppercase "SAMSUNG", the lowercase version is used in all legal aspects (e.g. on Wikipedia and in privacy/legal statements on https://www.samsung.com/semiconductor/privacy-global/). Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
192 lines
8.1 KiB
C
192 lines
8.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
|
|
//
|
|
// Copyright (c) 2011-2015 Samsung Electronics Co., Ltd.
|
|
// http://www.samsung.com/
|
|
//
|
|
// Exynos5250 - CPU PMU (Power Management Unit) support
|
|
|
|
#include <linux/soc/samsung/exynos-regs-pmu.h>
|
|
#include <linux/soc/samsung/exynos-pmu.h>
|
|
|
|
#include "exynos-pmu.h"
|
|
|
|
static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
|
|
/* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
|
|
{ EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
|
|
{ EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
{ EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
{ EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
|
|
{ EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
{ EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
{ EXYNOS5_FSYS_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
{ EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
{ EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
|
|
{ EXYNOS5_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} },
|
|
{ EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} },
|
|
{ EXYNOS_L2_OPTION(0), { 0x10, 0x10, 0x0 } },
|
|
{ EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
{ EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
{ EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
{ EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
{ EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
{ EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
{ EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
{ EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
{ EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
{ EXYNOS5_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
{ EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
{ EXYNOS5_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
{ EXYNOS5_TOP_PWR_SYS_PWR_REG, { 0x3, 0x0, 0x3} },
|
|
{ EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
{ EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
{ EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} },
|
|
{ EXYNOS5_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
{ EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
{ EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
{ EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
{ EXYNOS5_USBOTG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
{ EXYNOS5_G2D_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
{ EXYNOS5_USBDRD_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
{ EXYNOS5_SDMMC_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
{ EXYNOS5_CSSYS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
{ EXYNOS5_SECSS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
{ EXYNOS5_ROTATOR_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
{ EXYNOS5_INTRAM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
{ EXYNOS5_INTROM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
{ EXYNOS5_JPEG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
{ EXYNOS5_JPEG_MEM_OPTION, { 0x10, 0x10, 0x0} },
|
|
{ EXYNOS5_HSI_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
{ EXYNOS5_MCUIOP_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
{ EXYNOS5_SATA_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} },
|
|
{ EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
{ EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
{ EXYNOS5_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
{ EXYNOS5_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
{ EXYNOS5_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
{ EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x1} },
|
|
{ EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
|
|
{ EXYNOS5_GSCL_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
{ EXYNOS5_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
{ EXYNOS5_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
{ EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
{ EXYNOS5_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} },
|
|
{ EXYNOS5_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} },
|
|
{ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
{ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
{ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
|
|
{ EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
|
|
{ PMU_TABLE_END,},
|
|
};
|
|
|
|
static unsigned int const exynos5_list_both_cnt_feed[] = {
|
|
EXYNOS5_ARM_CORE0_OPTION,
|
|
EXYNOS5_ARM_CORE1_OPTION,
|
|
EXYNOS5_ARM_COMMON_OPTION,
|
|
EXYNOS5_GSCL_OPTION,
|
|
EXYNOS5_ISP_OPTION,
|
|
EXYNOS5_MFC_OPTION,
|
|
EXYNOS5_G3D_OPTION,
|
|
EXYNOS5_DISP1_OPTION,
|
|
EXYNOS5_MAU_OPTION,
|
|
EXYNOS5_TOP_PWR_OPTION,
|
|
EXYNOS5_TOP_PWR_SYSMEM_OPTION,
|
|
};
|
|
|
|
static unsigned int const exynos5_list_disable_wfi_wfe[] = {
|
|
EXYNOS5_ARM_CORE1_OPTION,
|
|
EXYNOS5_FSYS_ARM_OPTION,
|
|
EXYNOS5_ISP_ARM_OPTION,
|
|
};
|
|
|
|
static void exynos5250_pmu_init(void)
|
|
{
|
|
unsigned int value;
|
|
/*
|
|
* When SYS_WDTRESET is set, watchdog timer reset request
|
|
* is ignored by power management unit.
|
|
*/
|
|
value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
|
|
value &= ~EXYNOS5_SYS_WDTRESET;
|
|
pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
|
|
|
|
value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
|
|
value &= ~EXYNOS5_SYS_WDTRESET;
|
|
pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
|
|
}
|
|
|
|
static void exynos5_powerdown_conf(enum sys_powerdown mode)
|
|
{
|
|
unsigned int i;
|
|
unsigned int tmp;
|
|
|
|
/*
|
|
* Enable both SC_FEEDBACK and SC_COUNTER
|
|
*/
|
|
for (i = 0; i < ARRAY_SIZE(exynos5_list_both_cnt_feed); i++) {
|
|
tmp = pmu_raw_readl(exynos5_list_both_cnt_feed[i]);
|
|
tmp |= (EXYNOS5_USE_SC_FEEDBACK |
|
|
EXYNOS5_USE_SC_COUNTER);
|
|
pmu_raw_writel(tmp, exynos5_list_both_cnt_feed[i]);
|
|
}
|
|
|
|
/*
|
|
* SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
|
|
*/
|
|
tmp = pmu_raw_readl(EXYNOS5_ARM_COMMON_OPTION);
|
|
tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
|
|
pmu_raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
|
|
|
|
/*
|
|
* Disable WFI/WFE on XXX_OPTION
|
|
*/
|
|
for (i = 0; i < ARRAY_SIZE(exynos5_list_disable_wfi_wfe); i++) {
|
|
tmp = pmu_raw_readl(exynos5_list_disable_wfi_wfe[i]);
|
|
tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
|
|
EXYNOS5_OPTION_USE_STANDBYWFI);
|
|
pmu_raw_writel(tmp, exynos5_list_disable_wfi_wfe[i]);
|
|
}
|
|
}
|
|
|
|
const struct exynos_pmu_data exynos5250_pmu_data = {
|
|
.pmu_config = exynos5250_pmu_config,
|
|
.pmu_init = exynos5250_pmu_init,
|
|
.powerdown_conf = exynos5_powerdown_conf,
|
|
};
|