mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-13 08:46:45 +07:00
55db890a83
Many controllers have an upper limit on the number of blocks that can be transferred in one request. Allow the host drivers to specify this and make sure we avoid hitting this limit. Also change the max_sectors field to avoid confusion. This makes it map less directly to the block layer limits, but as they didn't apply directly on MMC cards anyway, this isn't a great loss. Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
704 lines
15 KiB
C
704 lines
15 KiB
C
/*
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* linux/drivers/mmc/mmci.c - ARM PrimeCell MMCI PL180/1 driver
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*
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* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/highmem.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/protocol.h>
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#include <linux/amba/bus.h>
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#include <linux/clk.h>
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#include <asm/cacheflush.h>
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#include <asm/div64.h>
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#include <asm/io.h>
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#include <asm/scatterlist.h>
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#include <asm/sizes.h>
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#include <asm/mach/mmc.h>
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#include "mmci.h"
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#define DRIVER_NAME "mmci-pl18x"
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#define DBG(host,fmt,args...) \
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pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args)
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static unsigned int fmax = 515633;
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static void
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mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
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{
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writel(0, host->base + MMCICOMMAND);
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BUG_ON(host->data);
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host->mrq = NULL;
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host->cmd = NULL;
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if (mrq->data)
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mrq->data->bytes_xfered = host->data_xfered;
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/*
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* Need to drop the host lock here; mmc_request_done may call
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* back into the driver...
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*/
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spin_unlock(&host->lock);
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mmc_request_done(host->mmc, mrq);
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spin_lock(&host->lock);
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}
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static void mmci_stop_data(struct mmci_host *host)
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{
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writel(0, host->base + MMCIDATACTRL);
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writel(0, host->base + MMCIMASK1);
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host->data = NULL;
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}
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static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
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{
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unsigned int datactrl, timeout, irqmask;
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unsigned long long clks;
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void __iomem *base;
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int blksz_bits;
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DBG(host, "blksz %04x blks %04x flags %08x\n",
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data->blksz, data->blocks, data->flags);
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host->data = data;
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host->size = data->blksz;
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host->data_xfered = 0;
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mmci_init_sg(host, data);
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clks = (unsigned long long)data->timeout_ns * host->cclk;
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do_div(clks, 1000000000UL);
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timeout = data->timeout_clks + (unsigned int)clks;
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base = host->base;
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writel(timeout, base + MMCIDATATIMER);
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writel(host->size, base + MMCIDATALENGTH);
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blksz_bits = ffs(data->blksz) - 1;
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BUG_ON(1 << blksz_bits != data->blksz);
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datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
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if (data->flags & MMC_DATA_READ) {
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datactrl |= MCI_DPSM_DIRECTION;
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irqmask = MCI_RXFIFOHALFFULLMASK;
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/*
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* If we have less than a FIFOSIZE of bytes to transfer,
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* trigger a PIO interrupt as soon as any data is available.
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*/
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if (host->size < MCI_FIFOSIZE)
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irqmask |= MCI_RXDATAAVLBLMASK;
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} else {
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/*
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* We don't actually need to include "FIFO empty" here
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* since its implicit in "FIFO half empty".
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*/
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irqmask = MCI_TXFIFOHALFEMPTYMASK;
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}
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writel(datactrl, base + MMCIDATACTRL);
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writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
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writel(irqmask, base + MMCIMASK1);
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}
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static void
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mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
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{
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void __iomem *base = host->base;
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DBG(host, "op %02x arg %08x flags %08x\n",
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cmd->opcode, cmd->arg, cmd->flags);
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if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
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writel(0, base + MMCICOMMAND);
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udelay(1);
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}
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c |= cmd->opcode | MCI_CPSM_ENABLE;
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if (cmd->flags & MMC_RSP_PRESENT) {
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if (cmd->flags & MMC_RSP_136)
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c |= MCI_CPSM_LONGRSP;
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c |= MCI_CPSM_RESPONSE;
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}
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if (/*interrupt*/0)
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c |= MCI_CPSM_INTERRUPT;
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host->cmd = cmd;
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writel(cmd->arg, base + MMCIARGUMENT);
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writel(c, base + MMCICOMMAND);
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}
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static void
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mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
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unsigned int status)
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{
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if (status & MCI_DATABLOCKEND) {
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host->data_xfered += data->blksz;
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}
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if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
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if (status & MCI_DATACRCFAIL)
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data->error = MMC_ERR_BADCRC;
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else if (status & MCI_DATATIMEOUT)
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data->error = MMC_ERR_TIMEOUT;
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else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN))
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data->error = MMC_ERR_FIFO;
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status |= MCI_DATAEND;
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/*
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* We hit an error condition. Ensure that any data
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* partially written to a page is properly coherent.
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*/
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if (host->sg_len && data->flags & MMC_DATA_READ)
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flush_dcache_page(host->sg_ptr->page);
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}
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if (status & MCI_DATAEND) {
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mmci_stop_data(host);
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if (!data->stop) {
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mmci_request_end(host, data->mrq);
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} else {
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mmci_start_command(host, data->stop, 0);
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}
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}
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}
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static void
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mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
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unsigned int status)
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{
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void __iomem *base = host->base;
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host->cmd = NULL;
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cmd->resp[0] = readl(base + MMCIRESPONSE0);
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cmd->resp[1] = readl(base + MMCIRESPONSE1);
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cmd->resp[2] = readl(base + MMCIRESPONSE2);
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cmd->resp[3] = readl(base + MMCIRESPONSE3);
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if (status & MCI_CMDTIMEOUT) {
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cmd->error = MMC_ERR_TIMEOUT;
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} else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
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cmd->error = MMC_ERR_BADCRC;
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}
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if (!cmd->data || cmd->error != MMC_ERR_NONE) {
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if (host->data)
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mmci_stop_data(host);
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mmci_request_end(host, cmd->mrq);
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} else if (!(cmd->data->flags & MMC_DATA_READ)) {
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mmci_start_data(host, cmd->data);
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}
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}
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static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
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{
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void __iomem *base = host->base;
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char *ptr = buffer;
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u32 status;
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do {
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int count = host->size - (readl(base + MMCIFIFOCNT) << 2);
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if (count > remain)
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count = remain;
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if (count <= 0)
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break;
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readsl(base + MMCIFIFO, ptr, count >> 2);
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ptr += count;
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remain -= count;
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if (remain == 0)
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break;
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status = readl(base + MMCISTATUS);
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} while (status & MCI_RXDATAAVLBL);
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return ptr - buffer;
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}
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static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
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{
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void __iomem *base = host->base;
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char *ptr = buffer;
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do {
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unsigned int count, maxcnt;
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maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE;
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count = min(remain, maxcnt);
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writesl(base + MMCIFIFO, ptr, count >> 2);
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ptr += count;
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remain -= count;
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if (remain == 0)
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break;
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status = readl(base + MMCISTATUS);
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} while (status & MCI_TXFIFOHALFEMPTY);
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return ptr - buffer;
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}
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/*
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* PIO data transfer IRQ handler.
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*/
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static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
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{
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struct mmci_host *host = dev_id;
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void __iomem *base = host->base;
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u32 status;
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status = readl(base + MMCISTATUS);
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DBG(host, "irq1 %08x\n", status);
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do {
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unsigned long flags;
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unsigned int remain, len;
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char *buffer;
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/*
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* For write, we only need to test the half-empty flag
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* here - if the FIFO is completely empty, then by
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* definition it is more than half empty.
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*
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* For read, check for data available.
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*/
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if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
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break;
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/*
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* Map the current scatter buffer.
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*/
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buffer = mmci_kmap_atomic(host, &flags) + host->sg_off;
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remain = host->sg_ptr->length - host->sg_off;
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len = 0;
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if (status & MCI_RXACTIVE)
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len = mmci_pio_read(host, buffer, remain);
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if (status & MCI_TXACTIVE)
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len = mmci_pio_write(host, buffer, remain, status);
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/*
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* Unmap the buffer.
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*/
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mmci_kunmap_atomic(host, buffer, &flags);
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host->sg_off += len;
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host->size -= len;
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remain -= len;
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if (remain)
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break;
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/*
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* If we were reading, and we have completed this
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* page, ensure that the data cache is coherent.
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*/
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if (status & MCI_RXACTIVE)
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flush_dcache_page(host->sg_ptr->page);
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if (!mmci_next_sg(host))
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break;
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status = readl(base + MMCISTATUS);
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} while (1);
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/*
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* If we're nearing the end of the read, switch to
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* "any data available" mode.
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*/
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if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE)
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writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
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/*
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* If we run out of data, disable the data IRQs; this
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* prevents a race where the FIFO becomes empty before
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* the chip itself has disabled the data path, and
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* stops us racing with our data end IRQ.
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*/
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if (host->size == 0) {
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writel(0, base + MMCIMASK1);
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writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
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}
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return IRQ_HANDLED;
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}
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/*
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* Handle completion of command and data transfers.
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*/
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static irqreturn_t mmci_irq(int irq, void *dev_id)
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{
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struct mmci_host *host = dev_id;
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u32 status;
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int ret = 0;
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spin_lock(&host->lock);
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do {
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struct mmc_command *cmd;
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struct mmc_data *data;
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status = readl(host->base + MMCISTATUS);
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status &= readl(host->base + MMCIMASK0);
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writel(status, host->base + MMCICLEAR);
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DBG(host, "irq0 %08x\n", status);
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data = host->data;
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if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
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MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
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mmci_data_irq(host, data, status);
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cmd = host->cmd;
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if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
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mmci_cmd_irq(host, cmd, status);
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ret = 1;
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} while (status);
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spin_unlock(&host->lock);
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return IRQ_RETVAL(ret);
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}
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static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
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{
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struct mmci_host *host = mmc_priv(mmc);
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WARN_ON(host->mrq != NULL);
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spin_lock_irq(&host->lock);
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host->mrq = mrq;
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if (mrq->data && mrq->data->flags & MMC_DATA_READ)
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mmci_start_data(host, mrq->data);
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mmci_start_command(host, mrq->cmd, 0);
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spin_unlock_irq(&host->lock);
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}
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static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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{
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struct mmci_host *host = mmc_priv(mmc);
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u32 clk = 0, pwr = 0;
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if (ios->clock) {
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if (ios->clock >= host->mclk) {
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clk = MCI_CLK_BYPASS;
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host->cclk = host->mclk;
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} else {
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clk = host->mclk / (2 * ios->clock) - 1;
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if (clk > 256)
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clk = 255;
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host->cclk = host->mclk / (2 * (clk + 1));
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}
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clk |= MCI_CLK_ENABLE;
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}
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if (host->plat->translate_vdd)
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pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
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switch (ios->power_mode) {
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case MMC_POWER_OFF:
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break;
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case MMC_POWER_UP:
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pwr |= MCI_PWR_UP;
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break;
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case MMC_POWER_ON:
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pwr |= MCI_PWR_ON;
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break;
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}
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if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
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pwr |= MCI_ROD;
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writel(clk, host->base + MMCICLOCK);
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if (host->pwr != pwr) {
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host->pwr = pwr;
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writel(pwr, host->base + MMCIPOWER);
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}
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}
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static const struct mmc_host_ops mmci_ops = {
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.request = mmci_request,
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.set_ios = mmci_set_ios,
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};
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static void mmci_check_status(unsigned long data)
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{
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struct mmci_host *host = (struct mmci_host *)data;
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unsigned int status;
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status = host->plat->status(mmc_dev(host->mmc));
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if (status ^ host->oldstat)
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mmc_detect_change(host->mmc, 0);
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host->oldstat = status;
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mod_timer(&host->timer, jiffies + HZ);
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}
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static int mmci_probe(struct amba_device *dev, void *id)
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{
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struct mmc_platform_data *plat = dev->dev.platform_data;
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struct mmci_host *host;
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struct mmc_host *mmc;
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int ret;
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/* must have platform data */
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if (!plat) {
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ret = -EINVAL;
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goto out;
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}
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ret = amba_request_regions(dev, DRIVER_NAME);
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if (ret)
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goto out;
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mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
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if (!mmc) {
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ret = -ENOMEM;
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goto rel_regions;
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}
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host = mmc_priv(mmc);
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host->clk = clk_get(&dev->dev, "MCLK");
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if (IS_ERR(host->clk)) {
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ret = PTR_ERR(host->clk);
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host->clk = NULL;
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goto host_free;
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}
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ret = clk_enable(host->clk);
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if (ret)
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goto clk_free;
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host->plat = plat;
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host->mclk = clk_get_rate(host->clk);
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host->mmc = mmc;
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host->base = ioremap(dev->res.start, SZ_4K);
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if (!host->base) {
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ret = -ENOMEM;
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goto clk_disable;
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}
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mmc->ops = &mmci_ops;
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mmc->f_min = (host->mclk + 511) / 512;
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mmc->f_max = min(host->mclk, fmax);
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mmc->ocr_avail = plat->ocr_mask;
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mmc->caps = MMC_CAP_MULTIWRITE;
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/*
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* We can do SGIO
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*/
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mmc->max_hw_segs = 16;
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mmc->max_phys_segs = NR_SG;
|
|
|
|
/*
|
|
* Since we only have a 16-bit data length register, we must
|
|
* ensure that we don't exceed 2^16-1 bytes in a single request.
|
|
*/
|
|
mmc->max_req_size = 65535;
|
|
|
|
/*
|
|
* Set the maximum segment size. Since we aren't doing DMA
|
|
* (yet) we are only limited by the data length register.
|
|
*/
|
|
mmc->max_seg_size = mmc->max_req_size;
|
|
|
|
/*
|
|
* Block size can be up to 2048 bytes, but must be a power of two.
|
|
*/
|
|
mmc->max_blk_size = 2048;
|
|
|
|
/*
|
|
* No limit on the number of blocks transferred.
|
|
*/
|
|
mmc->max_blk_count = mmc->max_req_size;
|
|
|
|
spin_lock_init(&host->lock);
|
|
|
|
writel(0, host->base + MMCIMASK0);
|
|
writel(0, host->base + MMCIMASK1);
|
|
writel(0xfff, host->base + MMCICLEAR);
|
|
|
|
ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
|
|
if (ret)
|
|
goto unmap;
|
|
|
|
ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, DRIVER_NAME " (pio)", host);
|
|
if (ret)
|
|
goto irq0_free;
|
|
|
|
writel(MCI_IRQENABLE, host->base + MMCIMASK0);
|
|
|
|
amba_set_drvdata(dev, mmc);
|
|
|
|
mmc_add_host(mmc);
|
|
|
|
printk(KERN_INFO "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n",
|
|
mmc_hostname(mmc), amba_rev(dev), amba_config(dev),
|
|
(unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]);
|
|
|
|
init_timer(&host->timer);
|
|
host->timer.data = (unsigned long)host;
|
|
host->timer.function = mmci_check_status;
|
|
host->timer.expires = jiffies + HZ;
|
|
add_timer(&host->timer);
|
|
|
|
return 0;
|
|
|
|
irq0_free:
|
|
free_irq(dev->irq[0], host);
|
|
unmap:
|
|
iounmap(host->base);
|
|
clk_disable:
|
|
clk_disable(host->clk);
|
|
clk_free:
|
|
clk_put(host->clk);
|
|
host_free:
|
|
mmc_free_host(mmc);
|
|
rel_regions:
|
|
amba_release_regions(dev);
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static int mmci_remove(struct amba_device *dev)
|
|
{
|
|
struct mmc_host *mmc = amba_get_drvdata(dev);
|
|
|
|
amba_set_drvdata(dev, NULL);
|
|
|
|
if (mmc) {
|
|
struct mmci_host *host = mmc_priv(mmc);
|
|
|
|
del_timer_sync(&host->timer);
|
|
|
|
mmc_remove_host(mmc);
|
|
|
|
writel(0, host->base + MMCIMASK0);
|
|
writel(0, host->base + MMCIMASK1);
|
|
|
|
writel(0, host->base + MMCICOMMAND);
|
|
writel(0, host->base + MMCIDATACTRL);
|
|
|
|
free_irq(dev->irq[0], host);
|
|
free_irq(dev->irq[1], host);
|
|
|
|
iounmap(host->base);
|
|
clk_disable(host->clk);
|
|
clk_put(host->clk);
|
|
|
|
mmc_free_host(mmc);
|
|
|
|
amba_release_regions(dev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int mmci_suspend(struct amba_device *dev, pm_message_t state)
|
|
{
|
|
struct mmc_host *mmc = amba_get_drvdata(dev);
|
|
int ret = 0;
|
|
|
|
if (mmc) {
|
|
struct mmci_host *host = mmc_priv(mmc);
|
|
|
|
ret = mmc_suspend_host(mmc, state);
|
|
if (ret == 0)
|
|
writel(0, host->base + MMCIMASK0);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int mmci_resume(struct amba_device *dev)
|
|
{
|
|
struct mmc_host *mmc = amba_get_drvdata(dev);
|
|
int ret = 0;
|
|
|
|
if (mmc) {
|
|
struct mmci_host *host = mmc_priv(mmc);
|
|
|
|
writel(MCI_IRQENABLE, host->base + MMCIMASK0);
|
|
|
|
ret = mmc_resume_host(mmc);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
#else
|
|
#define mmci_suspend NULL
|
|
#define mmci_resume NULL
|
|
#endif
|
|
|
|
static struct amba_id mmci_ids[] = {
|
|
{
|
|
.id = 0x00041180,
|
|
.mask = 0x000fffff,
|
|
},
|
|
{
|
|
.id = 0x00041181,
|
|
.mask = 0x000fffff,
|
|
},
|
|
{ 0, 0 },
|
|
};
|
|
|
|
static struct amba_driver mmci_driver = {
|
|
.drv = {
|
|
.name = DRIVER_NAME,
|
|
},
|
|
.probe = mmci_probe,
|
|
.remove = mmci_remove,
|
|
.suspend = mmci_suspend,
|
|
.resume = mmci_resume,
|
|
.id_table = mmci_ids,
|
|
};
|
|
|
|
static int __init mmci_init(void)
|
|
{
|
|
return amba_driver_register(&mmci_driver);
|
|
}
|
|
|
|
static void __exit mmci_exit(void)
|
|
{
|
|
amba_driver_unregister(&mmci_driver);
|
|
}
|
|
|
|
module_init(mmci_init);
|
|
module_exit(mmci_exit);
|
|
module_param(fmax, uint, 0444);
|
|
|
|
MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
|
|
MODULE_LICENSE("GPL");
|