mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 16:35:13 +07:00
81df84f406
The spec suggests waiting up to 500ms for the PHY to settle before testing link state, but practice shows that 100ms is sufficient (this is the delay value we also use on the other SH-4A PCI controllers, too). This makes device detection much more reliable, although in the future it should be a bit faster to simply serialize with a TLP IRQ. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
459 lines
11 KiB
C
459 lines
11 KiB
C
/*
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* Low-Level PCI Express Support for the SH7786
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*
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* Copyright (C) 2009 - 2010 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include "pcie-sh7786.h"
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#include <asm/sizes.h>
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struct sh7786_pcie_port {
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struct pci_channel *hose;
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unsigned int index;
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int endpoint;
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int link;
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};
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static struct sh7786_pcie_port *sh7786_pcie_ports;
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static unsigned int nr_ports;
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static struct sh7786_pcie_hwops {
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int (*core_init)(void);
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int (*port_init_hw)(struct sh7786_pcie_port *port);
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} *sh7786_pcie_hwops;
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static struct resource sh7786_pci0_resources[] = {
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{
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.name = "PCIe0 IO",
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.start = 0xfd000000,
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.end = 0xfd000000 + SZ_8M - 1,
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.flags = IORESOURCE_IO,
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}, {
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.name = "PCIe0 MEM 0",
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.start = 0xc0000000,
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.end = 0xc0000000 + SZ_512M - 1,
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
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}, {
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.name = "PCIe0 MEM 1",
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.start = 0x10000000,
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.end = 0x10000000 + SZ_64M - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.name = "PCIe0 MEM 2",
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.start = 0xfe100000,
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.end = 0xfe100000 + SZ_1M - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct resource sh7786_pci1_resources[] = {
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{
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.name = "PCIe1 IO",
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.start = 0xfd800000,
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.end = 0xfd800000 + SZ_8M - 1,
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.flags = IORESOURCE_IO,
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}, {
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.name = "PCIe1 MEM 0",
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.start = 0xa0000000,
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.end = 0xa0000000 + SZ_512M - 1,
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
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}, {
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.name = "PCIe1 MEM 1",
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.start = 0x30000000,
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.end = 0x30000000 + SZ_256M - 1,
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
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}, {
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.name = "PCIe1 MEM 2",
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.start = 0xfe300000,
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.end = 0xfe300000 + SZ_1M - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct resource sh7786_pci2_resources[] = {
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{
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.name = "PCIe2 IO",
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.start = 0xfc800000,
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.end = 0xfc800000 + SZ_4M - 1,
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.flags = IORESOURCE_IO,
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}, {
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.name = "PCIe2 MEM 0",
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.start = 0x80000000,
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.end = 0x80000000 + SZ_512M - 1,
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
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}, {
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.name = "PCIe2 MEM 1",
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.start = 0x20000000,
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.end = 0x20000000 + SZ_256M - 1,
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
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}, {
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.name = "PCIe2 MEM 2",
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.start = 0xfcd00000,
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.end = 0xfcd00000 + SZ_1M - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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extern struct pci_ops sh7786_pci_ops;
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#define DEFINE_CONTROLLER(start, idx) \
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{ \
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.pci_ops = &sh7786_pci_ops, \
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.resources = sh7786_pci##idx##_resources, \
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.nr_resources = ARRAY_SIZE(sh7786_pci##idx##_resources), \
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.reg_base = start, \
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.mem_offset = 0, \
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.io_offset = 0, \
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}
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static struct pci_channel sh7786_pci_channels[] = {
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DEFINE_CONTROLLER(0xfe000000, 0),
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DEFINE_CONTROLLER(0xfe200000, 1),
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DEFINE_CONTROLLER(0xfcc00000, 2),
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};
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static int phy_wait_for_ack(struct pci_channel *chan)
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{
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unsigned int timeout = 100;
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while (timeout--) {
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if (pci_read_reg(chan, SH4A_PCIEPHYADRR) & (1 << BITS_ACK))
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return 0;
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udelay(100);
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}
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return -ETIMEDOUT;
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}
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static int pci_wait_for_irq(struct pci_channel *chan, unsigned int mask)
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{
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unsigned int timeout = 100;
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while (timeout--) {
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if ((pci_read_reg(chan, SH4A_PCIEINTR) & mask) == mask)
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return 0;
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udelay(100);
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}
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return -ETIMEDOUT;
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}
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static void phy_write_reg(struct pci_channel *chan, unsigned int addr,
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unsigned int lane, unsigned int data)
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{
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unsigned long phyaddr;
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phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) +
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((addr & 0xff) << BITS_ADR);
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/* Set write data */
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pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR);
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pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR);
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phy_wait_for_ack(chan);
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/* Clear command */
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pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR);
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pci_write_reg(chan, 0, SH4A_PCIEPHYADRR);
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phy_wait_for_ack(chan);
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}
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static int phy_init(struct pci_channel *chan)
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{
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unsigned long ctrl;
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unsigned int timeout = 100;
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/* Enable clock */
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ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
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ctrl |= (1 << BITS_CKE);
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pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
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/* Initialize the phy */
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phy_write_reg(chan, 0x60, 0xf, 0x004b008b);
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phy_write_reg(chan, 0x61, 0xf, 0x00007b41);
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phy_write_reg(chan, 0x64, 0xf, 0x00ff4f00);
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phy_write_reg(chan, 0x65, 0xf, 0x09070907);
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phy_write_reg(chan, 0x66, 0xf, 0x00000010);
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phy_write_reg(chan, 0x74, 0xf, 0x0007001c);
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phy_write_reg(chan, 0x79, 0xf, 0x01fc000d);
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phy_write_reg(chan, 0xb0, 0xf, 0x00000610);
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/* Deassert Standby */
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phy_write_reg(chan, 0x67, 0x1, 0x00000400);
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/* Disable clock */
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ctrl = pci_read_reg(chan, SH4A_PCIEPHYCTLR);
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ctrl &= ~(1 << BITS_CKE);
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pci_write_reg(chan, ctrl, SH4A_PCIEPHYCTLR);
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while (timeout--) {
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if (pci_read_reg(chan, SH4A_PCIEPHYSR))
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return 0;
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udelay(100);
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}
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return -ETIMEDOUT;
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}
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static void pcie_reset(struct sh7786_pcie_port *port)
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{
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struct pci_channel *chan = port->hose;
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pci_write_reg(chan, 1, SH4A_PCIESRSTR);
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pci_write_reg(chan, 0, SH4A_PCIETCTLR);
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pci_write_reg(chan, 0, SH4A_PCIESRSTR);
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pci_write_reg(chan, 0, SH4A_PCIETXVC0SR);
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}
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static int pcie_init(struct sh7786_pcie_port *port)
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{
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struct pci_channel *chan = port->hose;
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unsigned int data;
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phys_addr_t memphys;
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size_t memsize;
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int ret, i, win;
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/* Begin initialization */
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pcie_reset(port);
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/* Initialize as type1. */
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data = pci_read_reg(chan, SH4A_PCIEPCICONF3);
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data &= ~(0x7f << 16);
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data |= PCI_HEADER_TYPE_BRIDGE << 16;
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pci_write_reg(chan, data, SH4A_PCIEPCICONF3);
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/* Initialize default capabilities. */
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data = pci_read_reg(chan, SH4A_PCIEEXPCAP0);
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data &= ~(PCI_EXP_FLAGS_TYPE << 16);
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if (port->endpoint)
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data |= PCI_EXP_TYPE_ENDPOINT << 20;
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else
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data |= PCI_EXP_TYPE_ROOT_PORT << 20;
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data |= PCI_CAP_ID_EXP;
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pci_write_reg(chan, data, SH4A_PCIEEXPCAP0);
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/* Enable data link layer active state reporting */
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pci_write_reg(chan, PCI_EXP_LNKCAP_DLLLARC, SH4A_PCIEEXPCAP3);
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/* Enable extended sync and ASPM L0s support */
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data = pci_read_reg(chan, SH4A_PCIEEXPCAP4);
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data &= ~PCI_EXP_LNKCTL_ASPMC;
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data |= PCI_EXP_LNKCTL_ES | 1;
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pci_write_reg(chan, data, SH4A_PCIEEXPCAP4);
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/* Write out the physical slot number */
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data = pci_read_reg(chan, SH4A_PCIEEXPCAP5);
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data &= ~PCI_EXP_SLTCAP_PSN;
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data |= (port->index + 1) << 19;
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pci_write_reg(chan, data, SH4A_PCIEEXPCAP5);
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/* Set the completion timer timeout to the maximum 32ms. */
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data = pci_read_reg(chan, SH4A_PCIETLCTLR);
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data &= ~0x3f00;
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data |= 0x32 << 8;
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pci_write_reg(chan, data, SH4A_PCIETLCTLR);
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/*
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* Set fast training sequences to the maximum 255,
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* and enable MAC data scrambling.
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*/
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data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
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data &= ~PCIEMACCTLR_SCR_DIS;
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data |= (0xff << 16);
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pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
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memphys = __pa(memory_start);
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memsize = roundup_pow_of_two(memory_end - memory_start);
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/*
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* If there's more than 512MB of memory, we need to roll over to
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* LAR1/LAMR1.
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*/
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if (memsize > SZ_512M) {
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__raw_writel(memphys + SZ_512M, chan->reg_base + SH4A_PCIELAR1);
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__raw_writel(((memsize - SZ_512M) - SZ_256) | 1,
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chan->reg_base + SH4A_PCIELAMR1);
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memsize = SZ_512M;
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} else {
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/*
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* Otherwise just zero it out and disable it.
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*/
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__raw_writel(0, chan->reg_base + SH4A_PCIELAR1);
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__raw_writel(0, chan->reg_base + SH4A_PCIELAMR1);
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}
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/*
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* LAR0/LAMR0 covers up to the first 512MB, which is enough to
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* cover all of lowmem on most platforms.
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*/
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__raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0);
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__raw_writel((memsize - SZ_256) | 1, chan->reg_base + SH4A_PCIELAMR0);
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__raw_writel(memphys, chan->reg_base + SH4A_PCIEPCICONF4);
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__raw_writel(0, chan->reg_base + SH4A_PCIEPCICONF5);
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/* Finish initialization */
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data = pci_read_reg(chan, SH4A_PCIETCTLR);
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data |= 0x1;
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pci_write_reg(chan, data, SH4A_PCIETCTLR);
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/* Let things settle down a bit.. */
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mdelay(100);
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/* Enable DL_Active Interrupt generation */
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data = pci_read_reg(chan, SH4A_PCIEDLINTENR);
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data |= PCIEDLINTENR_DLL_ACT_ENABLE;
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pci_write_reg(chan, data, SH4A_PCIEDLINTENR);
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/* Disable MAC data scrambling. */
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data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
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data |= PCIEMACCTLR_SCR_DIS | (0xff << 16);
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pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
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ret = pci_wait_for_irq(chan, MASK_INT_TX_CTRL);
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if (unlikely(ret != 0))
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return -ENODEV;
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data = pci_read_reg(chan, SH4A_PCIEPCICONF1);
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data &= ~(PCI_STATUS_DEVSEL_MASK << 16);
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data |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
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(PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_FAST) << 16;
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pci_write_reg(chan, data, SH4A_PCIEPCICONF1);
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pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR);
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pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR);
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wmb();
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data = pci_read_reg(chan, SH4A_PCIEMACSR);
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printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n",
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port->index, (data >> 20) & 0x3f);
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for (i = win = 0; i < chan->nr_resources; i++) {
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struct resource *res = chan->resources + i;
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resource_size_t size;
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u32 enable_mask;
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/*
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* We can't use the 32-bit mode windows in legacy 29-bit
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* mode, so just skip them entirely.
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*/
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if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode())
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continue;
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pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));
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size = resource_size(res);
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/*
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* The PAMR mask is calculated in units of 256kB, which
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* keeps things pretty simple.
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*/
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__raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
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chan->reg_base + SH4A_PCIEPAMR(win));
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pci_write_reg(chan, res->start, SH4A_PCIEPARL(win));
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pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(win));
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enable_mask = MASK_PARE;
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if (res->flags & IORESOURCE_IO)
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enable_mask |= MASK_SPC;
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pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(win));
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win++;
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}
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return 0;
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}
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int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
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{
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return 71;
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}
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static int sh7786_pcie_core_init(void)
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{
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/* Return the number of ports */
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return test_mode_pin(MODE_PIN12) ? 3 : 2;
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}
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static int __devinit sh7786_pcie_init_hw(struct sh7786_pcie_port *port)
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{
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int ret;
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ret = phy_init(port->hose);
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if (unlikely(ret < 0))
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return ret;
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/*
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* Check if we are configured in endpoint or root complex mode,
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* this is a fixed pin setting that applies to all PCIe ports.
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*/
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port->endpoint = test_mode_pin(MODE_PIN11);
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ret = pcie_init(port);
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if (unlikely(ret < 0))
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return ret;
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return register_pci_controller(port->hose);
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}
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static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
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.core_init = sh7786_pcie_core_init,
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.port_init_hw = sh7786_pcie_init_hw,
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};
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static int __init sh7786_pcie_init(void)
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{
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int ret = 0, i;
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printk(KERN_NOTICE "PCI: Starting initialization.\n");
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sh7786_pcie_hwops = &sh7786_65nm_pcie_hwops;
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nr_ports = sh7786_pcie_hwops->core_init();
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BUG_ON(nr_ports > ARRAY_SIZE(sh7786_pci_channels));
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if (unlikely(nr_ports == 0))
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return -ENODEV;
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sh7786_pcie_ports = kzalloc(nr_ports * sizeof(struct sh7786_pcie_port),
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GFP_KERNEL);
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if (unlikely(!sh7786_pcie_ports))
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return -ENOMEM;
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printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports);
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for (i = 0; i < nr_ports; i++) {
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struct sh7786_pcie_port *port = sh7786_pcie_ports + i;
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port->index = i;
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port->hose = sh7786_pci_channels + i;
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port->hose->io_map_base = port->hose->resources[0].start;
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ret |= sh7786_pcie_hwops->port_init_hw(port);
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}
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if (unlikely(ret))
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return ret;
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return 0;
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}
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arch_initcall(sh7786_pcie_init);
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