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44922150d8
If we have a series of events from userpsace, with %fprs=FPRS_FEF, like follows: ETRAP ETRAP VIS_ENTRY(fprs=0x4) VIS_EXIT RTRAP (kernel FPU restore with fpu_saved=0x4) RTRAP We will not restore the user registers that were clobbered by the FPU using kernel code in the inner-most trap. Traps allocate FPU save slots in the thread struct, and FPU using sequences save the "dirty" FPU registers only. This works at the initial trap level because all of the registers get recorded into the top-level FPU save area, and we'll return to userspace with the FPU disabled so that any FPU use by the user will take an FPU disabled trap wherein we'll load the registers back up properly. But this is not how trap returns from kernel to kernel operate. The simplest fix for this bug is to always save all FPU register state for anything other than the top-most FPU save area. Getting rid of the optimized inner-slot FPU saving code ends up making VISEntryHalf degenerate into plain VISEntry. Longer term we need to do something smarter to reinstate the partial save optimizations. Perhaps the fundament error is having trap entry and exit allocate FPU save slots and restore register state. Instead, the VISEntry et al. calls should be doing that work. This bug is about two decades old. Reported-by: James Y Knight <jyknight@google.com> Signed-off-by: David S. Miller <davem@davemloft.net>
67 lines
1.5 KiB
C
67 lines
1.5 KiB
C
#ifndef _SPARC64_VISASM_H
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#define _SPARC64_VISASM_H
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/* visasm.h: FPU saving macros for VIS routines
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*
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* Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#include <asm/pstate.h>
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#include <asm/ptrace.h>
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/* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc */
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#define VISEntry \
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rd %fprs, %o5; \
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andcc %o5, (FPRS_FEF|FPRS_DU), %g0; \
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be,pt %icc, 297f; \
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sethi %hi(297f), %g7; \
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sethi %hi(VISenter), %g1; \
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jmpl %g1 + %lo(VISenter), %g0; \
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or %g7, %lo(297f), %g7; \
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297: wr %g0, FPRS_FEF, %fprs; \
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#define VISExit \
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wr %g0, 0, %fprs;
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/* Clobbers %o5, %g1, %g2, %g3, %g7, %icc, %xcc.
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* Must preserve %o5 between VISEntryHalf and VISExitHalf */
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#define VISEntryHalf \
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VISEntry
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#define VISExitHalf \
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VISExit
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#define VISEntryHalfFast(fail_label) \
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rd %fprs, %o5; \
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andcc %o5, FPRS_FEF, %g0; \
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be,pt %icc, 297f; \
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nop; \
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ba,a,pt %xcc, fail_label; \
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297: wr %o5, FPRS_FEF, %fprs;
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#define VISExitHalfFast \
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wr %o5, 0, %fprs;
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#ifndef __ASSEMBLY__
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static inline void save_and_clear_fpu(void) {
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__asm__ __volatile__ (
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" rd %%fprs, %%o5\n"
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" andcc %%o5, %0, %%g0\n"
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" be,pt %%icc, 299f\n"
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" sethi %%hi(298f), %%g7\n"
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" sethi %%hi(VISenter), %%g1\n"
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" jmpl %%g1 + %%lo(VISenter), %%g0\n"
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" or %%g7, %%lo(298f), %%g7\n"
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" 298: wr %%g0, 0, %%fprs\n"
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" 299:\n"
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" " : : "i" (FPRS_FEF|FPRS_DU) :
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"o5", "g1", "g2", "g3", "g7", "cc");
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}
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int vis_emul(struct pt_regs *, unsigned int);
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#endif
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#endif /* _SPARC64_ASI_H */
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