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50dbabe06a
Print more information about MCE error whether it is an hardware or software error. Some of the MCE errors can be easily categorized as hardware or software errors e.g. UEs are due to hardware error, where as error triggered due to invalid usage of tlbie is a pure software bug. But not all the MCE errors can be easily categorize into either software or hardware. There are errors like multihit errors which are usually result of a software bug, but in some rare cases a hardware failure can cause a multihit error. In past, we have seen case where after replacing faulty chip, multihit errors stopped occurring. Same with parity errors, which are usually due to faulty hardware but there are chances where multihit can also cause an parity error. Such errors are difficult to determine what really caused it. Hence this patch classifies MCE errors into following four categorize: 1. Hardware error: UE and Link timeout failure errors. 2. Probable hardware error (some chance of software cause) SLB/ERAT/TLB Parity errors. 3. Software error Invalid tlbie form. 4. Probable software error (some chance of hardware cause) SLB/ERAT/TLB Multihit errors. Sample output: MCE: CPU80: machine check (Warning) Guest SLB Multihit DAR: 000001001b6e0320 [Recovered] MCE: CPU80: PID: 24765 Comm: qemu-system-ppc Guest NIP: [00007fffa309dc60] MCE: CPU80: Probable Software error (some chance of hardware cause) Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
647 lines
21 KiB
C
647 lines
21 KiB
C
/*
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* Machine check exception handling CPU-side for power7 and power8
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright 2013 IBM Corporation
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* Author: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
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*/
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#undef DEBUG
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#define pr_fmt(fmt) "mce_power: " fmt
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <asm/mmu.h>
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#include <asm/mce.h>
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#include <asm/machdep.h>
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#include <asm/pgtable.h>
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#include <asm/pte-walk.h>
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#include <asm/sstep.h>
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#include <asm/exception-64s.h>
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/*
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* Convert an address related to an mm to a PFN. NOTE: we are in real
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* mode, we could potentially race with page table updates.
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*/
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unsigned long addr_to_pfn(struct pt_regs *regs, unsigned long addr)
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{
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pte_t *ptep;
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unsigned long flags;
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struct mm_struct *mm;
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if (user_mode(regs))
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mm = current->mm;
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else
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mm = &init_mm;
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local_irq_save(flags);
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if (mm == current->mm)
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ptep = find_current_mm_pte(mm->pgd, addr, NULL, NULL);
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else
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ptep = find_init_mm_pte(addr, NULL);
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local_irq_restore(flags);
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if (!ptep || pte_special(*ptep))
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return ULONG_MAX;
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return pte_pfn(*ptep);
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}
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/* flush SLBs and reload */
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#ifdef CONFIG_PPC_BOOK3S_64
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void flush_and_reload_slb(void)
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{
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/* Invalidate all SLBs */
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slb_flush_all_realmode();
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#ifdef CONFIG_KVM_BOOK3S_HANDLER
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/*
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* If machine check is hit when in guest or in transition, we will
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* only flush the SLBs and continue.
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*/
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if (get_paca()->kvm_hstate.in_guest)
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return;
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#endif
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if (early_radix_enabled())
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return;
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/*
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* This probably shouldn't happen, but it may be possible it's
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* called in early boot before SLB shadows are allocated.
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*/
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if (!get_slb_shadow())
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return;
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slb_restore_bolted_realmode();
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}
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#endif
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static void flush_erat(void)
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{
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#ifdef CONFIG_PPC_BOOK3S_64
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if (!early_cpu_has_feature(CPU_FTR_ARCH_300)) {
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flush_and_reload_slb();
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return;
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}
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#endif
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/* PPC_INVALIDATE_ERAT can only be used on ISA v3 and newer */
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asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
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}
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#define MCE_FLUSH_SLB 1
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#define MCE_FLUSH_TLB 2
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#define MCE_FLUSH_ERAT 3
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static int mce_flush(int what)
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{
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#ifdef CONFIG_PPC_BOOK3S_64
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if (what == MCE_FLUSH_SLB) {
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flush_and_reload_slb();
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return 1;
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}
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#endif
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if (what == MCE_FLUSH_ERAT) {
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flush_erat();
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return 1;
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}
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if (what == MCE_FLUSH_TLB) {
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tlbiel_all();
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return 1;
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}
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return 0;
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}
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#define SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42))
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struct mce_ierror_table {
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unsigned long srr1_mask;
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unsigned long srr1_value;
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bool nip_valid; /* nip is a valid indicator of faulting address */
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unsigned int error_type;
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unsigned int error_subtype;
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unsigned int error_class;
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unsigned int initiator;
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unsigned int severity;
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bool sync_error;
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};
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static const struct mce_ierror_table mce_p7_ierror_table[] = {
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{ 0x00000000001c0000, 0x0000000000040000, true,
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MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00000000001c0000, 0x0000000000080000, true,
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MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00000000001c0000, 0x00000000000c0000, true,
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MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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{ 0x00000000001c0000, 0x0000000000100000, true,
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MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_INDETERMINATE, /* BOTH */
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MCE_ECLASS_SOFT_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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{ 0x00000000001c0000, 0x0000000000140000, true,
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MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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{ 0x00000000001c0000, 0x0000000000180000, true,
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MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00000000001c0000, 0x00000000001c0000, true,
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MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0, 0, 0, 0, 0, 0, 0 } };
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static const struct mce_ierror_table mce_p8_ierror_table[] = {
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{ 0x00000000081c0000, 0x0000000000040000, true,
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MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00000000081c0000, 0x0000000000080000, true,
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MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00000000081c0000, 0x00000000000c0000, true,
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MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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{ 0x00000000081c0000, 0x0000000000100000, true,
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MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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{ 0x00000000081c0000, 0x0000000000140000, true,
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MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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{ 0x00000000081c0000, 0x0000000000180000, true,
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MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH,
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MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00000000081c0000, 0x00000000001c0000, true,
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MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00000000081c0000, 0x0000000008000000, true,
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MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_IFETCH_TIMEOUT, MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00000000081c0000, 0x0000000008040000, true,
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MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT,
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MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0, 0, 0, 0, 0, 0, 0 } };
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static const struct mce_ierror_table mce_p9_ierror_table[] = {
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{ 0x00000000081c0000, 0x0000000000040000, true,
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MCE_ERROR_TYPE_UE, MCE_UE_ERROR_IFETCH, MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00000000081c0000, 0x0000000000080000, true,
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MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00000000081c0000, 0x00000000000c0000, true,
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MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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{ 0x00000000081c0000, 0x0000000000100000, true,
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MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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{ 0x00000000081c0000, 0x0000000000140000, true,
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MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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{ 0x00000000081c0000, 0x0000000000180000, true,
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MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00000000081c0000, 0x00000000001c0000, true,
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MCE_ERROR_TYPE_RA, MCE_RA_ERROR_IFETCH_FOREIGN, MCE_ECLASS_SOFTWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00000000081c0000, 0x0000000008000000, true,
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MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_IFETCH_TIMEOUT, MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00000000081c0000, 0x0000000008040000, true,
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MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_PAGE_TABLE_WALK_IFETCH_TIMEOUT,
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MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00000000081c0000, 0x00000000080c0000, true,
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MCE_ERROR_TYPE_RA, MCE_RA_ERROR_IFETCH, MCE_ECLASS_SOFTWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00000000081c0000, 0x0000000008100000, true,
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MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH, MCE_ECLASS_SOFTWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00000000081c0000, 0x0000000008140000, false,
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MCE_ERROR_TYPE_RA, MCE_RA_ERROR_STORE, MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_FATAL, false }, /* ASYNC is fatal */
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{ 0x00000000081c0000, 0x0000000008180000, false,
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MCE_ERROR_TYPE_LINK,MCE_LINK_ERROR_STORE_TIMEOUT,
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MCE_INITIATOR_CPU, MCE_SEV_FATAL, false }, /* ASYNC is fatal */
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{ 0x00000000081c0000, 0x00000000081c0000, true, MCE_ECLASS_HARDWARE,
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MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_IFETCH_FOREIGN,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0, 0, 0, 0, 0, 0, 0 } };
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struct mce_derror_table {
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unsigned long dsisr_value;
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bool dar_valid; /* dar is a valid indicator of faulting address */
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unsigned int error_type;
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unsigned int error_subtype;
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unsigned int error_class;
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unsigned int initiator;
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unsigned int severity;
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bool sync_error;
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};
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static const struct mce_derror_table mce_p7_derror_table[] = {
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{ 0x00008000, false,
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MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00004000, true,
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MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
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MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00000800, true,
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MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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{ 0x00000400, true,
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MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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{ 0x00000080, true,
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MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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{ 0x00000100, true,
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MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00000040, true,
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MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_INDETERMINATE, /* BOTH */
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MCE_ECLASS_HARD_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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{ 0, false, 0, 0, 0, 0, 0 } };
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static const struct mce_derror_table mce_p8_derror_table[] = {
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{ 0x00008000, false,
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MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00004000, true,
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MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
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MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00002000, true,
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MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_LOAD_TIMEOUT, MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00001000, true,
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MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT,
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MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00000800, true,
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MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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{ 0x00000400, true,
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MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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{ 0x00000200, true,
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MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, /* SECONDARY ERAT */
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MCE_ECLASS_SOFT_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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{ 0x00000080, true,
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MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, /* Before PARITY */
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MCE_ECLASS_SOFT_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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{ 0x00000100, true,
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MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0, false, 0, 0, 0, 0, 0 } };
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static const struct mce_derror_table mce_p9_derror_table[] = {
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{ 0x00008000, false,
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MCE_ERROR_TYPE_UE, MCE_UE_ERROR_LOAD_STORE, MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00004000, true,
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MCE_ERROR_TYPE_UE, MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
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MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00002000, true,
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MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_LOAD_TIMEOUT, MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00001000, true,
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MCE_ERROR_TYPE_LINK, MCE_LINK_ERROR_PAGE_TABLE_WALK_LOAD_STORE_TIMEOUT,
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MCE_ECLASS_HARDWARE,
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MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
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{ 0x00000800, true,
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MCE_ERROR_TYPE_ERAT, MCE_ERAT_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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{ 0x00000400, true,
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MCE_ERROR_TYPE_TLB, MCE_TLB_ERROR_MULTIHIT, MCE_ECLASS_SOFT_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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{ 0x00000200, false,
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MCE_ERROR_TYPE_USER, MCE_USER_ERROR_TLBIE, MCE_ECLASS_SOFTWARE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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{ 0x00000080, true,
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MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_MULTIHIT, /* Before PARITY */
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MCE_ECLASS_SOFT_INDETERMINATE,
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MCE_INITIATOR_CPU, MCE_SEV_WARNING, true },
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|
{ 0x00000100, true,
|
|
MCE_ERROR_TYPE_SLB, MCE_SLB_ERROR_PARITY, MCE_ECLASS_HARD_INDETERMINATE,
|
|
MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
|
|
{ 0x00000040, true,
|
|
MCE_ERROR_TYPE_RA, MCE_RA_ERROR_LOAD, MCE_ECLASS_HARDWARE,
|
|
MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
|
|
{ 0x00000020, false,
|
|
MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE,
|
|
MCE_ECLASS_HARDWARE,
|
|
MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
|
|
{ 0x00000010, false,
|
|
MCE_ERROR_TYPE_RA, MCE_RA_ERROR_PAGE_TABLE_WALK_LOAD_STORE_FOREIGN,
|
|
MCE_ECLASS_HARDWARE,
|
|
MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
|
|
{ 0x00000008, false,
|
|
MCE_ERROR_TYPE_RA, MCE_RA_ERROR_LOAD_STORE_FOREIGN, MCE_ECLASS_HARDWARE,
|
|
MCE_INITIATOR_CPU, MCE_SEV_SEVERE, true },
|
|
{ 0, false, 0, 0, 0, 0, 0 } };
|
|
|
|
static int mce_find_instr_ea_and_pfn(struct pt_regs *regs, uint64_t *addr,
|
|
uint64_t *phys_addr)
|
|
{
|
|
/*
|
|
* Carefully look at the NIP to determine
|
|
* the instruction to analyse. Reading the NIP
|
|
* in real-mode is tricky and can lead to recursive
|
|
* faults
|
|
*/
|
|
int instr;
|
|
unsigned long pfn, instr_addr;
|
|
struct instruction_op op;
|
|
struct pt_regs tmp = *regs;
|
|
|
|
pfn = addr_to_pfn(regs, regs->nip);
|
|
if (pfn != ULONG_MAX) {
|
|
instr_addr = (pfn << PAGE_SHIFT) + (regs->nip & ~PAGE_MASK);
|
|
instr = *(unsigned int *)(instr_addr);
|
|
if (!analyse_instr(&op, &tmp, instr)) {
|
|
pfn = addr_to_pfn(regs, op.ea);
|
|
*addr = op.ea;
|
|
*phys_addr = (pfn << PAGE_SHIFT);
|
|
return 0;
|
|
}
|
|
/*
|
|
* analyse_instr() might fail if the instruction
|
|
* is not a load/store, although this is unexpected
|
|
* for load/store errors or if we got the NIP
|
|
* wrong
|
|
*/
|
|
}
|
|
*addr = 0;
|
|
return -1;
|
|
}
|
|
|
|
static int mce_handle_ierror(struct pt_regs *regs,
|
|
const struct mce_ierror_table table[],
|
|
struct mce_error_info *mce_err, uint64_t *addr,
|
|
uint64_t *phys_addr)
|
|
{
|
|
uint64_t srr1 = regs->msr;
|
|
int handled = 0;
|
|
int i;
|
|
|
|
*addr = 0;
|
|
|
|
for (i = 0; table[i].srr1_mask; i++) {
|
|
if ((srr1 & table[i].srr1_mask) != table[i].srr1_value)
|
|
continue;
|
|
|
|
/* attempt to correct the error */
|
|
switch (table[i].error_type) {
|
|
case MCE_ERROR_TYPE_SLB:
|
|
handled = mce_flush(MCE_FLUSH_SLB);
|
|
break;
|
|
case MCE_ERROR_TYPE_ERAT:
|
|
handled = mce_flush(MCE_FLUSH_ERAT);
|
|
break;
|
|
case MCE_ERROR_TYPE_TLB:
|
|
handled = mce_flush(MCE_FLUSH_TLB);
|
|
break;
|
|
}
|
|
|
|
/* now fill in mce_error_info */
|
|
mce_err->error_type = table[i].error_type;
|
|
mce_err->error_class = table[i].error_class;
|
|
switch (table[i].error_type) {
|
|
case MCE_ERROR_TYPE_UE:
|
|
mce_err->u.ue_error_type = table[i].error_subtype;
|
|
break;
|
|
case MCE_ERROR_TYPE_SLB:
|
|
mce_err->u.slb_error_type = table[i].error_subtype;
|
|
break;
|
|
case MCE_ERROR_TYPE_ERAT:
|
|
mce_err->u.erat_error_type = table[i].error_subtype;
|
|
break;
|
|
case MCE_ERROR_TYPE_TLB:
|
|
mce_err->u.tlb_error_type = table[i].error_subtype;
|
|
break;
|
|
case MCE_ERROR_TYPE_USER:
|
|
mce_err->u.user_error_type = table[i].error_subtype;
|
|
break;
|
|
case MCE_ERROR_TYPE_RA:
|
|
mce_err->u.ra_error_type = table[i].error_subtype;
|
|
break;
|
|
case MCE_ERROR_TYPE_LINK:
|
|
mce_err->u.link_error_type = table[i].error_subtype;
|
|
break;
|
|
}
|
|
mce_err->sync_error = table[i].sync_error;
|
|
mce_err->severity = table[i].severity;
|
|
mce_err->initiator = table[i].initiator;
|
|
if (table[i].nip_valid) {
|
|
*addr = regs->nip;
|
|
if (mce_err->sync_error &&
|
|
table[i].error_type == MCE_ERROR_TYPE_UE) {
|
|
unsigned long pfn;
|
|
|
|
if (get_paca()->in_mce < MAX_MCE_DEPTH) {
|
|
pfn = addr_to_pfn(regs, regs->nip);
|
|
if (pfn != ULONG_MAX) {
|
|
*phys_addr =
|
|
(pfn << PAGE_SHIFT);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return handled;
|
|
}
|
|
|
|
mce_err->error_type = MCE_ERROR_TYPE_UNKNOWN;
|
|
mce_err->error_class = MCE_ECLASS_UNKNOWN;
|
|
mce_err->severity = MCE_SEV_SEVERE;
|
|
mce_err->initiator = MCE_INITIATOR_CPU;
|
|
mce_err->sync_error = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mce_handle_derror(struct pt_regs *regs,
|
|
const struct mce_derror_table table[],
|
|
struct mce_error_info *mce_err, uint64_t *addr,
|
|
uint64_t *phys_addr)
|
|
{
|
|
uint64_t dsisr = regs->dsisr;
|
|
int handled = 0;
|
|
int found = 0;
|
|
int i;
|
|
|
|
*addr = 0;
|
|
|
|
for (i = 0; table[i].dsisr_value; i++) {
|
|
if (!(dsisr & table[i].dsisr_value))
|
|
continue;
|
|
|
|
/* attempt to correct the error */
|
|
switch (table[i].error_type) {
|
|
case MCE_ERROR_TYPE_SLB:
|
|
if (mce_flush(MCE_FLUSH_SLB))
|
|
handled = 1;
|
|
break;
|
|
case MCE_ERROR_TYPE_ERAT:
|
|
if (mce_flush(MCE_FLUSH_ERAT))
|
|
handled = 1;
|
|
break;
|
|
case MCE_ERROR_TYPE_TLB:
|
|
if (mce_flush(MCE_FLUSH_TLB))
|
|
handled = 1;
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* Attempt to handle multiple conditions, but only return
|
|
* one. Ensure uncorrectable errors are first in the table
|
|
* to match.
|
|
*/
|
|
if (found)
|
|
continue;
|
|
|
|
/* now fill in mce_error_info */
|
|
mce_err->error_type = table[i].error_type;
|
|
mce_err->error_class = table[i].error_class;
|
|
switch (table[i].error_type) {
|
|
case MCE_ERROR_TYPE_UE:
|
|
mce_err->u.ue_error_type = table[i].error_subtype;
|
|
break;
|
|
case MCE_ERROR_TYPE_SLB:
|
|
mce_err->u.slb_error_type = table[i].error_subtype;
|
|
break;
|
|
case MCE_ERROR_TYPE_ERAT:
|
|
mce_err->u.erat_error_type = table[i].error_subtype;
|
|
break;
|
|
case MCE_ERROR_TYPE_TLB:
|
|
mce_err->u.tlb_error_type = table[i].error_subtype;
|
|
break;
|
|
case MCE_ERROR_TYPE_USER:
|
|
mce_err->u.user_error_type = table[i].error_subtype;
|
|
break;
|
|
case MCE_ERROR_TYPE_RA:
|
|
mce_err->u.ra_error_type = table[i].error_subtype;
|
|
break;
|
|
case MCE_ERROR_TYPE_LINK:
|
|
mce_err->u.link_error_type = table[i].error_subtype;
|
|
break;
|
|
}
|
|
mce_err->sync_error = table[i].sync_error;
|
|
mce_err->severity = table[i].severity;
|
|
mce_err->initiator = table[i].initiator;
|
|
if (table[i].dar_valid)
|
|
*addr = regs->dar;
|
|
else if (mce_err->sync_error &&
|
|
table[i].error_type == MCE_ERROR_TYPE_UE) {
|
|
/*
|
|
* We do a maximum of 4 nested MCE calls, see
|
|
* kernel/exception-64s.h
|
|
*/
|
|
if (get_paca()->in_mce < MAX_MCE_DEPTH)
|
|
mce_find_instr_ea_and_pfn(regs, addr, phys_addr);
|
|
}
|
|
found = 1;
|
|
}
|
|
|
|
if (found)
|
|
return handled;
|
|
|
|
mce_err->error_type = MCE_ERROR_TYPE_UNKNOWN;
|
|
mce_err->error_class = MCE_ECLASS_UNKNOWN;
|
|
mce_err->severity = MCE_SEV_SEVERE;
|
|
mce_err->initiator = MCE_INITIATOR_CPU;
|
|
mce_err->sync_error = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static long mce_handle_ue_error(struct pt_regs *regs)
|
|
{
|
|
long handled = 0;
|
|
|
|
/*
|
|
* On specific SCOM read via MMIO we may get a machine check
|
|
* exception with SRR0 pointing inside opal. If that is the
|
|
* case OPAL may have recovery address to re-read SCOM data in
|
|
* different way and hence we can recover from this MC.
|
|
*/
|
|
|
|
if (ppc_md.mce_check_early_recovery) {
|
|
if (ppc_md.mce_check_early_recovery(regs))
|
|
handled = 1;
|
|
}
|
|
return handled;
|
|
}
|
|
|
|
static long mce_handle_error(struct pt_regs *regs,
|
|
const struct mce_derror_table dtable[],
|
|
const struct mce_ierror_table itable[])
|
|
{
|
|
struct mce_error_info mce_err = { 0 };
|
|
uint64_t addr, phys_addr = ULONG_MAX;
|
|
uint64_t srr1 = regs->msr;
|
|
long handled;
|
|
|
|
if (SRR1_MC_LOADSTORE(srr1))
|
|
handled = mce_handle_derror(regs, dtable, &mce_err, &addr,
|
|
&phys_addr);
|
|
else
|
|
handled = mce_handle_ierror(regs, itable, &mce_err, &addr,
|
|
&phys_addr);
|
|
|
|
if (!handled && mce_err.error_type == MCE_ERROR_TYPE_UE)
|
|
handled = mce_handle_ue_error(regs);
|
|
|
|
save_mce_event(regs, handled, &mce_err, regs->nip, addr, phys_addr);
|
|
|
|
return handled;
|
|
}
|
|
|
|
long __machine_check_early_realmode_p7(struct pt_regs *regs)
|
|
{
|
|
/* P7 DD1 leaves top bits of DSISR undefined */
|
|
regs->dsisr &= 0x0000ffff;
|
|
|
|
return mce_handle_error(regs, mce_p7_derror_table, mce_p7_ierror_table);
|
|
}
|
|
|
|
long __machine_check_early_realmode_p8(struct pt_regs *regs)
|
|
{
|
|
return mce_handle_error(regs, mce_p8_derror_table, mce_p8_ierror_table);
|
|
}
|
|
|
|
long __machine_check_early_realmode_p9(struct pt_regs *regs)
|
|
{
|
|
/*
|
|
* On POWER9 DD2.1 and below, it's possible to get a machine check
|
|
* caused by a paste instruction where only DSISR bit 25 is set. This
|
|
* will result in the MCE handler seeing an unknown event and the kernel
|
|
* crashing. An MCE that occurs like this is spurious, so we don't need
|
|
* to do anything in terms of servicing it. If there is something that
|
|
* needs to be serviced, the CPU will raise the MCE again with the
|
|
* correct DSISR so that it can be serviced properly. So detect this
|
|
* case and mark it as handled.
|
|
*/
|
|
if (SRR1_MC_LOADSTORE(regs->msr) && regs->dsisr == 0x02000000)
|
|
return 1;
|
|
|
|
return mce_handle_error(regs, mce_p9_derror_table, mce_p9_ierror_table);
|
|
}
|