mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 11:06:48 +07:00
ca5a1b9ba0
- Accurate frontbuffer tracking and frontbuffer rendering invalidate, flush and flip events. This is prep work for proper PSR support and should also be useful for DRRS&fbc. - Runtime suspend hardware on system suspend to support the new SOix sleep states, from Jesse. - PSR updates for broadwell (Rodrigo) - Universal plane support for cursors (Matt Roper), including core drm patches. - Prefault gtt mappings (Chris) - baytrail write-enable pte bit support (Akash Goel) - mmio based flips (Sourab Gupta) instead of blitter ring flips - interrupt handling race fixes (Oscar Mateo) And old, not yet merged features from the previous round: - rps/turbo support for chv (Deepak) - some other straggling chv patches (Ville) - proper universal plane conversion for the primary plane (Matt Roper) - ppgtt on vlv from Jesse - pile of cleanups, little fixes for insane corner cases and improved debug support all over * tag 'drm-intel-next-2014-06-20' of git://anongit.freedesktop.org/drm-intel: (99 commits) drm/i915: Update DRIVER_DATE to 20140620 drivers/i915: Fix unnoticed failure of init_ring_common() drm/i915: Track frontbuffer invalidation/flushing drm/i915: Use new frontbuffer bits to increase pll clock drm/i915: don't take runtime PM reference around freeze/thaw drm/i915: use runtime irq suspend/resume in freeze/thaw drm/i915: Properly track domain of the fbcon fb drm/i915: Print obj->frontbuffer_bits in debugfs output drm/i915: Introduce accurate frontbuffer tracking drm/i915: Drop schedule_back from psr_exit drm/i915: Ditch intel_edp_psr_update drm/i915: Drop unecessary complexity from psr_inactivate drm/i915: Remove ctx->last_ring drm/i915/chv: Ack interrupts before handling them (CHV) drm/i915/bdw: Ack interrupts before handling them (GEN8) drm/i915/vlv: Ack interrupts before handling them (VLV) drm/i915: Ack interrupts before handling them (GEN5 - GEN7) drm/i915: Don't BUG_ON in i915_gem_obj_offset drm/i915: Grab dev->struct_mutex in i915_gem_pageflip_info drm/i915: Add some L3 registers to the parser whitelist ... Conflicts: drivers/gpu/drm/i915/i915_drv.c
810 lines
23 KiB
C
810 lines
23 KiB
C
/*
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* Copyright © 2011-2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Ben Widawsky <ben@bwidawsk.net>
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*
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*/
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/*
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* This file implements HW context support. On gen5+ a HW context consists of an
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* opaque GPU object which is referenced at times of context saves and restores.
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* With RC6 enabled, the context is also referenced as the GPU enters and exists
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* from RC6 (GPU has it's own internal power context, except on gen5). Though
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* something like a context does exist for the media ring, the code only
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* supports contexts for the render ring.
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*
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* In software, there is a distinction between contexts created by the user,
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* and the default HW context. The default HW context is used by GPU clients
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* that do not request setup of their own hardware context. The default
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* context's state is never restored to help prevent programming errors. This
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* would happen if a client ran and piggy-backed off another clients GPU state.
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* The default context only exists to give the GPU some offset to load as the
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* current to invoke a save of the context we actually care about. In fact, the
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* code could likely be constructed, albeit in a more complicated fashion, to
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* never use the default context, though that limits the driver's ability to
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* swap out, and/or destroy other contexts.
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*
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* All other contexts are created as a request by the GPU client. These contexts
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* store GPU state, and thus allow GPU clients to not re-emit state (and
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* potentially query certain state) at any time. The kernel driver makes
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* certain that the appropriate commands are inserted.
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*
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* The context life cycle is semi-complicated in that context BOs may live
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* longer than the context itself because of the way the hardware, and object
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* tracking works. Below is a very crude representation of the state machine
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* describing the context life.
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* refcount pincount active
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* S0: initial state 0 0 0
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* S1: context created 1 0 0
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* S2: context is currently running 2 1 X
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* S3: GPU referenced, but not current 2 0 1
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* S4: context is current, but destroyed 1 1 0
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* S5: like S3, but destroyed 1 0 1
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*
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* The most common (but not all) transitions:
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* S0->S1: client creates a context
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* S1->S2: client submits execbuf with context
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* S2->S3: other clients submits execbuf with context
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* S3->S1: context object was retired
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* S3->S2: clients submits another execbuf
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* S2->S4: context destroy called with current context
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* S3->S5->S0: destroy path
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* S4->S5->S0: destroy path on current context
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*
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* There are two confusing terms used above:
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* The "current context" means the context which is currently running on the
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* GPU. The GPU has loaded its state already and has stored away the gtt
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* offset of the BO. The GPU is not actively referencing the data at this
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* offset, but it will on the next context switch. The only way to avoid this
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* is to do a GPU reset.
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*
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* An "active context' is one which was previously the "current context" and is
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* on the active list waiting for the next context switch to occur. Until this
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* happens, the object must remain at the same gtt offset. It is therefore
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* possible to destroy a context, but it is still active.
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*
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*/
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#include <drm/drmP.h>
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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/* This is a HW constraint. The value below is the largest known requirement
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* I've seen in a spec to date, and that was a workaround for a non-shipping
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* part. It should be safe to decrease this, but it's more future proof as is.
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*/
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#define GEN6_CONTEXT_ALIGN (64<<10)
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#define GEN7_CONTEXT_ALIGN 4096
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static void do_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt)
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{
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struct drm_device *dev = ppgtt->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct i915_address_space *vm = &ppgtt->base;
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if (ppgtt == dev_priv->mm.aliasing_ppgtt ||
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(list_empty(&vm->active_list) && list_empty(&vm->inactive_list))) {
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ppgtt->base.cleanup(&ppgtt->base);
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return;
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}
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/*
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* Make sure vmas are unbound before we take down the drm_mm
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*
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* FIXME: Proper refcounting should take care of this, this shouldn't be
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* needed at all.
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*/
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if (!list_empty(&vm->active_list)) {
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struct i915_vma *vma;
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list_for_each_entry(vma, &vm->active_list, mm_list)
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if (WARN_ON(list_empty(&vma->vma_link) ||
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list_is_singular(&vma->vma_link)))
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break;
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i915_gem_evict_vm(&ppgtt->base, true);
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} else {
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i915_gem_retire_requests(dev);
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i915_gem_evict_vm(&ppgtt->base, false);
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}
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ppgtt->base.cleanup(&ppgtt->base);
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}
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static void ppgtt_release(struct kref *kref)
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{
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struct i915_hw_ppgtt *ppgtt =
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container_of(kref, struct i915_hw_ppgtt, ref);
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do_ppgtt_cleanup(ppgtt);
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kfree(ppgtt);
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}
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static size_t get_context_alignment(struct drm_device *dev)
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{
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if (IS_GEN6(dev))
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return GEN6_CONTEXT_ALIGN;
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return GEN7_CONTEXT_ALIGN;
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}
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static int get_context_size(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int ret;
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u32 reg;
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switch (INTEL_INFO(dev)->gen) {
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case 6:
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reg = I915_READ(CXT_SIZE);
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ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
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break;
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case 7:
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reg = I915_READ(GEN7_CXT_SIZE);
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if (IS_HASWELL(dev))
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ret = HSW_CXT_TOTAL_SIZE;
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else
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ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
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break;
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case 8:
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ret = GEN8_CXT_TOTAL_SIZE;
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break;
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default:
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BUG();
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}
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return ret;
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}
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void i915_gem_context_free(struct kref *ctx_ref)
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{
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struct intel_context *ctx = container_of(ctx_ref,
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typeof(*ctx), ref);
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struct i915_hw_ppgtt *ppgtt = NULL;
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if (ctx->obj) {
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/* We refcount even the aliasing PPGTT to keep the code symmetric */
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if (USES_PPGTT(ctx->obj->base.dev))
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ppgtt = ctx_to_ppgtt(ctx);
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/* XXX: Free up the object before tearing down the address space, in
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* case we're bound in the PPGTT */
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drm_gem_object_unreference(&ctx->obj->base);
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}
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if (ppgtt)
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kref_put(&ppgtt->ref, ppgtt_release);
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list_del(&ctx->link);
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kfree(ctx);
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}
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static struct i915_hw_ppgtt *
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create_vm_for_ctx(struct drm_device *dev, struct intel_context *ctx)
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{
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struct i915_hw_ppgtt *ppgtt;
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int ret;
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ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
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if (!ppgtt)
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return ERR_PTR(-ENOMEM);
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ret = i915_gem_init_ppgtt(dev, ppgtt);
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if (ret) {
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kfree(ppgtt);
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return ERR_PTR(ret);
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}
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ppgtt->ctx = ctx;
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return ppgtt;
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}
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static struct intel_context *
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__create_hw_context(struct drm_device *dev,
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struct drm_i915_file_private *file_priv)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_context *ctx;
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int ret;
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ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
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if (ctx == NULL)
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return ERR_PTR(-ENOMEM);
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kref_init(&ctx->ref);
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list_add_tail(&ctx->link, &dev_priv->context_list);
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if (dev_priv->hw_context_size) {
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ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size);
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if (ctx->obj == NULL) {
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ret = -ENOMEM;
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goto err_out;
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}
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/*
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* Try to make the context utilize L3 as well as LLC.
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*
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* On VLV we don't have L3 controls in the PTEs so we
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* shouldn't touch the cache level, especially as that
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* would make the object snooped which might have a
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* negative performance impact.
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*/
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if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) {
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ret = i915_gem_object_set_cache_level(ctx->obj,
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I915_CACHE_L3_LLC);
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/* Failure shouldn't ever happen this early */
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if (WARN_ON(ret))
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goto err_out;
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}
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}
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/* Default context will never have a file_priv */
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if (file_priv != NULL) {
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ret = idr_alloc(&file_priv->context_idr, ctx,
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DEFAULT_CONTEXT_ID, 0, GFP_KERNEL);
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if (ret < 0)
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goto err_out;
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} else
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ret = DEFAULT_CONTEXT_ID;
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ctx->file_priv = file_priv;
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ctx->id = ret;
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/* NB: Mark all slices as needing a remap so that when the context first
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* loads it will restore whatever remap state already exists. If there
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* is no remap info, it will be a NOP. */
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ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1;
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return ctx;
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err_out:
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i915_gem_context_unreference(ctx);
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return ERR_PTR(ret);
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}
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/**
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* The default context needs to exist per ring that uses contexts. It stores the
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* context state of the GPU for applications that don't utilize HW contexts, as
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* well as an idle case.
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*/
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static struct intel_context *
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i915_gem_create_context(struct drm_device *dev,
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struct drm_i915_file_private *file_priv,
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bool create_vm)
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{
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const bool is_global_default_ctx = file_priv == NULL;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_context *ctx;
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int ret = 0;
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BUG_ON(!mutex_is_locked(&dev->struct_mutex));
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ctx = __create_hw_context(dev, file_priv);
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if (IS_ERR(ctx))
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return ctx;
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if (is_global_default_ctx && ctx->obj) {
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/* We may need to do things with the shrinker which
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* require us to immediately switch back to the default
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* context. This can cause a problem as pinning the
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* default context also requires GTT space which may not
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* be available. To avoid this we always pin the default
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* context.
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*/
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ret = i915_gem_obj_ggtt_pin(ctx->obj,
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get_context_alignment(dev), 0);
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if (ret) {
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DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
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goto err_destroy;
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}
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}
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if (create_vm) {
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struct i915_hw_ppgtt *ppgtt = create_vm_for_ctx(dev, ctx);
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if (IS_ERR_OR_NULL(ppgtt)) {
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DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
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PTR_ERR(ppgtt));
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ret = PTR_ERR(ppgtt);
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goto err_unpin;
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} else
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ctx->vm = &ppgtt->base;
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/* This case is reserved for the global default context and
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* should only happen once. */
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if (is_global_default_ctx) {
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if (WARN_ON(dev_priv->mm.aliasing_ppgtt)) {
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ret = -EEXIST;
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goto err_unpin;
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}
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dev_priv->mm.aliasing_ppgtt = ppgtt;
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}
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} else if (USES_PPGTT(dev)) {
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/* For platforms which only have aliasing PPGTT, we fake the
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* address space and refcounting. */
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ctx->vm = &dev_priv->mm.aliasing_ppgtt->base;
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kref_get(&dev_priv->mm.aliasing_ppgtt->ref);
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} else
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ctx->vm = &dev_priv->gtt.base;
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return ctx;
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err_unpin:
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if (is_global_default_ctx && ctx->obj)
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i915_gem_object_ggtt_unpin(ctx->obj);
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err_destroy:
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i915_gem_context_unreference(ctx);
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return ERR_PTR(ret);
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}
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void i915_gem_context_reset(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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/* Prevent the hardware from restoring the last context (which hung) on
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* the next switch */
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for (i = 0; i < I915_NUM_RINGS; i++) {
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struct intel_engine_cs *ring = &dev_priv->ring[i];
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struct intel_context *dctx = ring->default_context;
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/* Do a fake switch to the default context */
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if (ring->last_context == dctx)
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continue;
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if (!ring->last_context)
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continue;
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if (dctx->obj && i == RCS) {
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WARN_ON(i915_gem_obj_ggtt_pin(dctx->obj,
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get_context_alignment(dev), 0));
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/* Fake a finish/inactive */
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dctx->obj->base.write_domain = 0;
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dctx->obj->active = 0;
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}
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i915_gem_context_unreference(ring->last_context);
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i915_gem_context_reference(dctx);
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ring->last_context = dctx;
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}
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}
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int i915_gem_context_init(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_context *ctx;
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int i;
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/* Init should only be called once per module load. Eventually the
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* restriction on the context_disabled check can be loosened. */
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if (WARN_ON(dev_priv->ring[RCS].default_context))
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return 0;
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if (HAS_HW_CONTEXTS(dev)) {
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dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
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if (dev_priv->hw_context_size > (1<<20)) {
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DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
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dev_priv->hw_context_size);
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dev_priv->hw_context_size = 0;
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}
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}
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ctx = i915_gem_create_context(dev, NULL, USES_PPGTT(dev));
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if (IS_ERR(ctx)) {
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DRM_ERROR("Failed to create default global context (error %ld)\n",
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PTR_ERR(ctx));
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return PTR_ERR(ctx);
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}
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/* NB: RCS will hold a ref for all rings */
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for (i = 0; i < I915_NUM_RINGS; i++)
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dev_priv->ring[i].default_context = ctx;
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DRM_DEBUG_DRIVER("%s context support initialized\n", dev_priv->hw_context_size ? "HW" : "fake");
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return 0;
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}
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void i915_gem_context_fini(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_context *dctx = dev_priv->ring[RCS].default_context;
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int i;
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if (dctx->obj) {
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/* The only known way to stop the gpu from accessing the hw context is
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* to reset it. Do this as the very last operation to avoid confusing
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* other code, leading to spurious errors. */
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intel_gpu_reset(dev);
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/* When default context is created and switched to, base object refcount
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* will be 2 (+1 from object creation and +1 from do_switch()).
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* i915_gem_context_fini() will be called after gpu_idle() has switched
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* to default context. So we need to unreference the base object once
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* to offset the do_switch part, so that i915_gem_context_unreference()
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* can then free the base object correctly. */
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WARN_ON(!dev_priv->ring[RCS].last_context);
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if (dev_priv->ring[RCS].last_context == dctx) {
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/* Fake switch to NULL context */
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WARN_ON(dctx->obj->active);
|
|
i915_gem_object_ggtt_unpin(dctx->obj);
|
|
i915_gem_context_unreference(dctx);
|
|
dev_priv->ring[RCS].last_context = NULL;
|
|
}
|
|
|
|
i915_gem_object_ggtt_unpin(dctx->obj);
|
|
}
|
|
|
|
for (i = 0; i < I915_NUM_RINGS; i++) {
|
|
struct intel_engine_cs *ring = &dev_priv->ring[i];
|
|
|
|
if (ring->last_context)
|
|
i915_gem_context_unreference(ring->last_context);
|
|
|
|
ring->default_context = NULL;
|
|
ring->last_context = NULL;
|
|
}
|
|
|
|
i915_gem_context_unreference(dctx);
|
|
}
|
|
|
|
int i915_gem_context_enable(struct drm_i915_private *dev_priv)
|
|
{
|
|
struct intel_engine_cs *ring;
|
|
int ret, i;
|
|
|
|
/* This is the only place the aliasing PPGTT gets enabled, which means
|
|
* it has to happen before we bail on reset */
|
|
if (dev_priv->mm.aliasing_ppgtt) {
|
|
struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
|
|
ppgtt->enable(ppgtt);
|
|
}
|
|
|
|
/* FIXME: We should make this work, even in reset */
|
|
if (i915_reset_in_progress(&dev_priv->gpu_error))
|
|
return 0;
|
|
|
|
BUG_ON(!dev_priv->ring[RCS].default_context);
|
|
|
|
for_each_ring(ring, dev_priv, i) {
|
|
ret = i915_switch_context(ring, ring->default_context);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int context_idr_cleanup(int id, void *p, void *data)
|
|
{
|
|
struct intel_context *ctx = p;
|
|
|
|
i915_gem_context_unreference(ctx);
|
|
return 0;
|
|
}
|
|
|
|
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file)
|
|
{
|
|
struct drm_i915_file_private *file_priv = file->driver_priv;
|
|
struct intel_context *ctx;
|
|
|
|
idr_init(&file_priv->context_idr);
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
ctx = i915_gem_create_context(dev, file_priv, USES_FULL_PPGTT(dev));
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
if (IS_ERR(ctx)) {
|
|
idr_destroy(&file_priv->context_idr);
|
|
return PTR_ERR(ctx);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
|
|
{
|
|
struct drm_i915_file_private *file_priv = file->driver_priv;
|
|
|
|
idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
|
|
idr_destroy(&file_priv->context_idr);
|
|
}
|
|
|
|
struct intel_context *
|
|
i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
|
|
{
|
|
struct intel_context *ctx;
|
|
|
|
ctx = (struct intel_context *)idr_find(&file_priv->context_idr, id);
|
|
if (!ctx)
|
|
return ERR_PTR(-ENOENT);
|
|
|
|
return ctx;
|
|
}
|
|
|
|
static inline int
|
|
mi_set_context(struct intel_engine_cs *ring,
|
|
struct intel_context *new_context,
|
|
u32 hw_flags)
|
|
{
|
|
int ret;
|
|
|
|
/* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
|
|
* invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
|
|
* explicitly, so we rely on the value at ring init, stored in
|
|
* itlb_before_ctx_switch.
|
|
*/
|
|
if (IS_GEN6(ring->dev)) {
|
|
ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
ret = intel_ring_begin(ring, 6);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
|
|
if (INTEL_INFO(ring->dev)->gen >= 7)
|
|
intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
|
|
else
|
|
intel_ring_emit(ring, MI_NOOP);
|
|
|
|
intel_ring_emit(ring, MI_NOOP);
|
|
intel_ring_emit(ring, MI_SET_CONTEXT);
|
|
intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->obj) |
|
|
MI_MM_SPACE_GTT |
|
|
MI_SAVE_EXT_STATE_EN |
|
|
MI_RESTORE_EXT_STATE_EN |
|
|
hw_flags);
|
|
/*
|
|
* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
|
|
* WaMiSetContext_Hang:snb,ivb,vlv
|
|
*/
|
|
intel_ring_emit(ring, MI_NOOP);
|
|
|
|
if (INTEL_INFO(ring->dev)->gen >= 7)
|
|
intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
|
|
else
|
|
intel_ring_emit(ring, MI_NOOP);
|
|
|
|
intel_ring_advance(ring);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int do_switch(struct intel_engine_cs *ring,
|
|
struct intel_context *to)
|
|
{
|
|
struct drm_i915_private *dev_priv = ring->dev->dev_private;
|
|
struct intel_context *from = ring->last_context;
|
|
struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(to);
|
|
u32 hw_flags = 0;
|
|
bool uninitialized = false;
|
|
int ret, i;
|
|
|
|
if (from != NULL && ring == &dev_priv->ring[RCS]) {
|
|
BUG_ON(from->obj == NULL);
|
|
BUG_ON(!i915_gem_obj_is_pinned(from->obj));
|
|
}
|
|
|
|
if (from == to && !to->remap_slice)
|
|
return 0;
|
|
|
|
/* Trying to pin first makes error handling easier. */
|
|
if (ring == &dev_priv->ring[RCS]) {
|
|
ret = i915_gem_obj_ggtt_pin(to->obj,
|
|
get_context_alignment(ring->dev), 0);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* Pin can switch back to the default context if we end up calling into
|
|
* evict_everything - as a last ditch gtt defrag effort that also
|
|
* switches to the default context. Hence we need to reload from here.
|
|
*/
|
|
from = ring->last_context;
|
|
|
|
if (USES_FULL_PPGTT(ring->dev)) {
|
|
ret = ppgtt->switch_mm(ppgtt, ring, false);
|
|
if (ret)
|
|
goto unpin_out;
|
|
}
|
|
|
|
if (ring != &dev_priv->ring[RCS]) {
|
|
if (from)
|
|
i915_gem_context_unreference(from);
|
|
goto done;
|
|
}
|
|
|
|
/*
|
|
* Clear this page out of any CPU caches for coherent swap-in/out. Note
|
|
* that thanks to write = false in this call and us not setting any gpu
|
|
* write domains when putting a context object onto the active list
|
|
* (when switching away from it), this won't block.
|
|
*
|
|
* XXX: We need a real interface to do this instead of trickery.
|
|
*/
|
|
ret = i915_gem_object_set_to_gtt_domain(to->obj, false);
|
|
if (ret)
|
|
goto unpin_out;
|
|
|
|
if (!to->obj->has_global_gtt_mapping) {
|
|
struct i915_vma *vma = i915_gem_obj_to_vma(to->obj,
|
|
&dev_priv->gtt.base);
|
|
vma->bind_vma(vma, to->obj->cache_level, GLOBAL_BIND);
|
|
}
|
|
|
|
if (!to->is_initialized || i915_gem_context_is_default(to))
|
|
hw_flags |= MI_RESTORE_INHIBIT;
|
|
|
|
ret = mi_set_context(ring, to, hw_flags);
|
|
if (ret)
|
|
goto unpin_out;
|
|
|
|
for (i = 0; i < MAX_L3_SLICES; i++) {
|
|
if (!(to->remap_slice & (1<<i)))
|
|
continue;
|
|
|
|
ret = i915_gem_l3_remap(ring, i);
|
|
/* If it failed, try again next round */
|
|
if (ret)
|
|
DRM_DEBUG_DRIVER("L3 remapping failed\n");
|
|
else
|
|
to->remap_slice &= ~(1<<i);
|
|
}
|
|
|
|
/* The backing object for the context is done after switching to the
|
|
* *next* context. Therefore we cannot retire the previous context until
|
|
* the next context has already started running. In fact, the below code
|
|
* is a bit suboptimal because the retiring can occur simply after the
|
|
* MI_SET_CONTEXT instead of when the next seqno has completed.
|
|
*/
|
|
if (from != NULL) {
|
|
from->obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
|
|
i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->obj), ring);
|
|
/* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
|
|
* whole damn pipeline, we don't need to explicitly mark the
|
|
* object dirty. The only exception is that the context must be
|
|
* correct in case the object gets swapped out. Ideally we'd be
|
|
* able to defer doing this until we know the object would be
|
|
* swapped, but there is no way to do that yet.
|
|
*/
|
|
from->obj->dirty = 1;
|
|
BUG_ON(from->obj->ring != ring);
|
|
|
|
/* obj is kept alive until the next request by its active ref */
|
|
i915_gem_object_ggtt_unpin(from->obj);
|
|
i915_gem_context_unreference(from);
|
|
}
|
|
|
|
uninitialized = !to->is_initialized && from == NULL;
|
|
to->is_initialized = true;
|
|
|
|
done:
|
|
i915_gem_context_reference(to);
|
|
ring->last_context = to;
|
|
|
|
if (uninitialized) {
|
|
ret = i915_gem_render_state_init(ring);
|
|
if (ret)
|
|
DRM_ERROR("init render state: %d\n", ret);
|
|
}
|
|
|
|
return 0;
|
|
|
|
unpin_out:
|
|
if (ring->id == RCS)
|
|
i915_gem_object_ggtt_unpin(to->obj);
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* i915_switch_context() - perform a GPU context switch.
|
|
* @ring: ring for which we'll execute the context switch
|
|
* @to: the context to switch to
|
|
*
|
|
* The context life cycle is simple. The context refcount is incremented and
|
|
* decremented by 1 and create and destroy. If the context is in use by the GPU,
|
|
* it will have a refoucnt > 1. This allows us to destroy the context abstract
|
|
* object while letting the normal object tracking destroy the backing BO.
|
|
*/
|
|
int i915_switch_context(struct intel_engine_cs *ring,
|
|
struct intel_context *to)
|
|
{
|
|
struct drm_i915_private *dev_priv = ring->dev->dev_private;
|
|
|
|
WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
|
|
|
|
if (to->obj == NULL) { /* We have the fake context */
|
|
if (to != ring->last_context) {
|
|
i915_gem_context_reference(to);
|
|
if (ring->last_context)
|
|
i915_gem_context_unreference(ring->last_context);
|
|
ring->last_context = to;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
return do_switch(ring, to);
|
|
}
|
|
|
|
static bool hw_context_enabled(struct drm_device *dev)
|
|
{
|
|
return to_i915(dev)->hw_context_size;
|
|
}
|
|
|
|
int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file)
|
|
{
|
|
struct drm_i915_gem_context_create *args = data;
|
|
struct drm_i915_file_private *file_priv = file->driver_priv;
|
|
struct intel_context *ctx;
|
|
int ret;
|
|
|
|
if (!hw_context_enabled(dev))
|
|
return -ENODEV;
|
|
|
|
ret = i915_mutex_lock_interruptible(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ctx = i915_gem_create_context(dev, file_priv, USES_FULL_PPGTT(dev));
|
|
mutex_unlock(&dev->struct_mutex);
|
|
if (IS_ERR(ctx))
|
|
return PTR_ERR(ctx);
|
|
|
|
args->ctx_id = ctx->id;
|
|
DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file)
|
|
{
|
|
struct drm_i915_gem_context_destroy *args = data;
|
|
struct drm_i915_file_private *file_priv = file->driver_priv;
|
|
struct intel_context *ctx;
|
|
int ret;
|
|
|
|
if (args->ctx_id == DEFAULT_CONTEXT_ID)
|
|
return -ENOENT;
|
|
|
|
ret = i915_mutex_lock_interruptible(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ctx = i915_gem_context_get(file_priv, args->ctx_id);
|
|
if (IS_ERR(ctx)) {
|
|
mutex_unlock(&dev->struct_mutex);
|
|
return PTR_ERR(ctx);
|
|
}
|
|
|
|
idr_remove(&ctx->file_priv->context_idr, ctx->id);
|
|
i915_gem_context_unreference(ctx);
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);
|
|
return 0;
|
|
}
|