mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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9ed68785f7
[Needed for HSDK]
Currently the first page of system (hence RAM base) is assumed to be
@ CONFIG_LINUX_LINK_BASE, where kernel itself is linked.
However is case of HSDK platform, for reasons explained in that patch,
this is not true. kernel needs to be linked @ 0x9000_0000 while DDR
is still wired at 0x8000_0000. To properly account for this 256M of RAM,
we need to introduce a new option and base page frame accountiing off of
it.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
[vgupta: renamed CONFIG_KERNEL_RAM_BASE_ADDRESS => CONFIG_LINUX_RAM_BASE
: simplified changelog]
71 lines
1.5 KiB
Plaintext
71 lines
1.5 KiB
Plaintext
/*
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* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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/include/ "skeleton_hs.dtsi"
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/ {
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model = "snps,nsim_hs";
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compatible = "snps,nsim_hs";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&core_intc>;
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memory {
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device_type = "memory";
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/* CONFIG_LINUX_RAM_BASE needs to match low mem start */
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reg = <0x0 0x80000000 0x0 0x20000000 /* 512 MB low mem */
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0x1 0x00000000 0x0 0x40000000>; /* 1 GB highmem */
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};
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chosen {
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bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8";
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};
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aliases {
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serial0 = &arcuart0;
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};
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fpga {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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/* only perip space at end of low mem accessible
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bus addr, parent bus addr, size */
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ranges = <0x80000000 0x0 0x80000000 0x80000000>;
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core_clk: core_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <80000000>;
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};
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core_intc: core-interrupt-controller {
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compatible = "snps,archs-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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arcuart0: serial@c0fc1000 {
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compatible = "snps,arc-uart";
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reg = <0xc0fc1000 0x100>;
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interrupts = <24>;
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clock-frequency = <80000000>;
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current-speed = <115200>;
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status = "okay";
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};
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arcpct0: pct {
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compatible = "snps,archs-pct";
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#interrupt-cells = <1>;
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interrupts = <20>;
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};
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};
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};
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