mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 23:26:45 +07:00
955c1cab80
Commit de79f7b9f6 ("powerpc: Put FP/VSX and VR state into structures")
modified load_up_fpu() and load_up_altivec() in such a way that they
now use r7 and r8. Unfortunately, the callers of these functions on
32-bit machines then return to userspace via fast_exception_return,
which doesn't restore all of the volatile GPRs, but only r1, r3 -- r6
and r9 -- r12. This was causing userspace segfaults and other
userspace misbehaviour on 32-bit machines.
This fixes the problem by changing the register usage of load_up_fpu()
and load_up_altivec() to avoid using r7 and r8 and instead use r6 and
r10. This also adds comments to those functions saying which registers
may be used.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Tested-by: Scott Wood <scottwood@freescale.com> (on e500mc, so no altivec)
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
477 lines
10 KiB
ArmAsm
477 lines
10 KiB
ArmAsm
#include <asm/processor.h>
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#include <asm/ppc_asm.h>
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#include <asm/reg.h>
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#include <asm/asm-offsets.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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/* void do_load_up_transact_altivec(struct thread_struct *thread)
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*
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* This is similar to load_up_altivec but for the transactional version of the
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* vector regs. It doesn't mess with the task MSR or valid flags.
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* Furthermore, VEC laziness is not supported with TM currently.
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*/
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_GLOBAL(do_load_up_transact_altivec)
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mfmsr r6
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oris r5,r6,MSR_VEC@h
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MTMSRD(r5)
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isync
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li r4,1
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stw r4,THREAD_USED_VR(r3)
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li r10,THREAD_TRANSACT_VRSTATE+VRSTATE_VSCR
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lvx vr0,r10,r3
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mtvscr vr0
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addi r10,r3,THREAD_TRANSACT_VRSTATE
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REST_32VRS(0,r4,r10)
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/* Disable VEC again. */
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MTMSRD(r6)
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isync
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blr
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#endif
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/*
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* Load state from memory into VMX registers including VSCR.
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* Assumes the caller has enabled VMX in the MSR.
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*/
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_GLOBAL(load_vr_state)
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li r4,VRSTATE_VSCR
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lvx vr0,r4,r3
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mtvscr vr0
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REST_32VRS(0,r4,r3)
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blr
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/*
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* Store VMX state into memory, including VSCR.
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* Assumes the caller has enabled VMX in the MSR.
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*/
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_GLOBAL(store_vr_state)
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SAVE_32VRS(0, r4, r3)
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mfvscr vr0
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li r4, VRSTATE_VSCR
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stvx vr0, r4, r3
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blr
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/*
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* Disable VMX for the task which had it previously,
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* and save its vector registers in its thread_struct.
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* Enables the VMX for use in the kernel on return.
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* On SMP we know the VMX is free, since we give it up every
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* switch (ie, no lazy save of the vector registers).
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*
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* Note that on 32-bit this can only use registers that will be
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* restored by fast_exception_return, i.e. r3 - r6, r10 and r11.
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*/
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_GLOBAL(load_up_altivec)
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mfmsr r5 /* grab the current MSR */
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oris r5,r5,MSR_VEC@h
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MTMSRD(r5) /* enable use of AltiVec now */
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isync
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/*
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* For SMP, we don't do lazy VMX switching because it just gets too
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* horrendously complex, especially when a task switches from one CPU
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* to another. Instead we call giveup_altvec in switch_to.
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* VRSAVE isn't dealt with here, that is done in the normal context
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* switch code. Note that we could rely on vrsave value to eventually
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* avoid saving all of the VREGs here...
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*/
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#ifndef CONFIG_SMP
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LOAD_REG_ADDRBASE(r3, last_task_used_altivec)
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toreal(r3)
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PPC_LL r4,ADDROFF(last_task_used_altivec)(r3)
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PPC_LCMPI 0,r4,0
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beq 1f
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/* Save VMX state to last_task_used_altivec's THREAD struct */
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toreal(r4)
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addi r4,r4,THREAD
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addi r6,r4,THREAD_VRSTATE
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SAVE_32VRS(0,r5,r6)
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mfvscr vr0
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li r10,VRSTATE_VSCR
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stvx vr0,r10,r6
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/* Disable VMX for last_task_used_altivec */
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PPC_LL r5,PT_REGS(r4)
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toreal(r5)
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PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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lis r10,MSR_VEC@h
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andc r4,r4,r10
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PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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1:
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#endif /* CONFIG_SMP */
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/* Hack: if we get an altivec unavailable trap with VRSAVE
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* set to all zeros, we assume this is a broken application
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* that fails to set it properly, and thus we switch it to
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* all 1's
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*/
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mfspr r4,SPRN_VRSAVE
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cmpwi 0,r4,0
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bne+ 1f
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li r4,-1
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mtspr SPRN_VRSAVE,r4
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1:
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/* enable use of VMX after return */
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#ifdef CONFIG_PPC32
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mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
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oris r9,r9,MSR_VEC@h
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#else
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ld r4,PACACURRENT(r13)
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addi r5,r4,THREAD /* Get THREAD */
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oris r12,r12,MSR_VEC@h
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std r12,_MSR(r1)
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#endif
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addi r6,r5,THREAD_VRSTATE
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li r4,1
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li r10,VRSTATE_VSCR
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stw r4,THREAD_USED_VR(r5)
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lvx vr0,r10,r6
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mtvscr vr0
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REST_32VRS(0,r4,r6)
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#ifndef CONFIG_SMP
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/* Update last_task_used_altivec to 'current' */
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subi r4,r5,THREAD /* Back to 'current' */
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fromreal(r4)
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PPC_STL r4,ADDROFF(last_task_used_altivec)(r3)
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#endif /* CONFIG_SMP */
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/* restore registers and return */
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blr
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_GLOBAL(giveup_altivec_notask)
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mfmsr r3
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andis. r4,r3,MSR_VEC@h
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bnelr /* Already enabled? */
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oris r3,r3,MSR_VEC@h
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SYNC
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MTMSRD(r3) /* enable use of VMX now */
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isync
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blr
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/*
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* giveup_altivec(tsk)
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* Disable VMX for the task given as the argument,
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* and save the vector registers in its thread_struct.
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* Enables the VMX for use in the kernel on return.
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*/
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_GLOBAL(giveup_altivec)
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mfmsr r5
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oris r5,r5,MSR_VEC@h
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SYNC
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MTMSRD(r5) /* enable use of VMX now */
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isync
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PPC_LCMPI 0,r3,0
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beqlr /* if no previous owner, done */
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addi r3,r3,THREAD /* want THREAD of task */
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PPC_LL r7,THREAD_VRSAVEAREA(r3)
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PPC_LL r5,PT_REGS(r3)
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PPC_LCMPI 0,r7,0
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bne 2f
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addi r7,r3,THREAD_VRSTATE
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2: PPC_LCMPI 0,r5,0
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SAVE_32VRS(0,r4,r7)
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mfvscr vr0
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li r4,VRSTATE_VSCR
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stvx vr0,r4,r7
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beq 1f
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PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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#ifdef CONFIG_VSX
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BEGIN_FTR_SECTION
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lis r3,(MSR_VEC|MSR_VSX)@h
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FTR_SECTION_ELSE
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lis r3,MSR_VEC@h
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_VSX)
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#else
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lis r3,MSR_VEC@h
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#endif
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andc r4,r4,r3 /* disable FP for previous task */
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PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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1:
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#ifndef CONFIG_SMP
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li r5,0
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LOAD_REG_ADDRBASE(r4,last_task_used_altivec)
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PPC_STL r5,ADDROFF(last_task_used_altivec)(r4)
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#endif /* CONFIG_SMP */
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blr
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#ifdef CONFIG_VSX
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#ifdef CONFIG_PPC32
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#error This asm code isn't ready for 32-bit kernels
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#endif
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/*
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* load_up_vsx(unused, unused, tsk)
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* Disable VSX for the task which had it previously,
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* and save its vector registers in its thread_struct.
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* Reuse the fp and vsx saves, but first check to see if they have
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* been saved already.
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*/
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_GLOBAL(load_up_vsx)
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/* Load FP and VSX registers if they haven't been done yet */
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andi. r5,r12,MSR_FP
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beql+ load_up_fpu /* skip if already loaded */
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andis. r5,r12,MSR_VEC@h
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beql+ load_up_altivec /* skip if already loaded */
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#ifndef CONFIG_SMP
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ld r3,last_task_used_vsx@got(r2)
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ld r4,0(r3)
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cmpdi 0,r4,0
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beq 1f
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/* Disable VSX for last_task_used_vsx */
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addi r4,r4,THREAD
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ld r5,PT_REGS(r4)
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ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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lis r6,MSR_VSX@h
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andc r6,r4,r6
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std r6,_MSR-STACK_FRAME_OVERHEAD(r5)
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1:
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#endif /* CONFIG_SMP */
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ld r4,PACACURRENT(r13)
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addi r4,r4,THREAD /* Get THREAD */
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li r6,1
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stw r6,THREAD_USED_VSR(r4) /* ... also set thread used vsr */
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/* enable use of VSX after return */
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oris r12,r12,MSR_VSX@h
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std r12,_MSR(r1)
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#ifndef CONFIG_SMP
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/* Update last_task_used_vsx to 'current' */
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ld r4,PACACURRENT(r13)
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std r4,0(r3)
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#endif /* CONFIG_SMP */
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b fast_exception_return
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/*
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* __giveup_vsx(tsk)
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* Disable VSX for the task given as the argument.
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* Does NOT save vsx registers.
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* Enables the VSX for use in the kernel on return.
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*/
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_GLOBAL(__giveup_vsx)
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mfmsr r5
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oris r5,r5,MSR_VSX@h
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mtmsrd r5 /* enable use of VSX now */
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isync
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cmpdi 0,r3,0
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beqlr- /* if no previous owner, done */
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addi r3,r3,THREAD /* want THREAD of task */
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ld r5,PT_REGS(r3)
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cmpdi 0,r5,0
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beq 1f
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ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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lis r3,MSR_VSX@h
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andc r4,r4,r3 /* disable VSX for previous task */
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std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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1:
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#ifndef CONFIG_SMP
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li r5,0
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ld r4,last_task_used_vsx@got(r2)
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std r5,0(r4)
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#endif /* CONFIG_SMP */
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blr
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#endif /* CONFIG_VSX */
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/*
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* The routines below are in assembler so we can closely control the
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* usage of floating-point registers. These routines must be called
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* with preempt disabled.
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*/
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#ifdef CONFIG_PPC32
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.data
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fpzero:
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.long 0
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fpone:
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.long 0x3f800000 /* 1.0 in single-precision FP */
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fphalf:
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.long 0x3f000000 /* 0.5 in single-precision FP */
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#define LDCONST(fr, name) \
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lis r11,name@ha; \
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lfs fr,name@l(r11)
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#else
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.section ".toc","aw"
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fpzero:
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.tc FD_0_0[TC],0
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fpone:
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.tc FD_3ff00000_0[TC],0x3ff0000000000000 /* 1.0 */
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fphalf:
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.tc FD_3fe00000_0[TC],0x3fe0000000000000 /* 0.5 */
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#define LDCONST(fr, name) \
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lfd fr,name@toc(r2)
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#endif
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.text
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/*
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* Internal routine to enable floating point and set FPSCR to 0.
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* Don't call it from C; it doesn't use the normal calling convention.
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*/
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fpenable:
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#ifdef CONFIG_PPC32
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stwu r1,-64(r1)
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#else
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stdu r1,-64(r1)
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#endif
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mfmsr r10
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ori r11,r10,MSR_FP
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mtmsr r11
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isync
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stfd fr0,24(r1)
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stfd fr1,16(r1)
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stfd fr31,8(r1)
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LDCONST(fr1, fpzero)
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mffs fr31
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MTFSF_L(fr1)
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blr
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fpdisable:
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mtlr r12
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MTFSF_L(fr31)
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lfd fr31,8(r1)
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lfd fr1,16(r1)
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lfd fr0,24(r1)
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mtmsr r10
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isync
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addi r1,r1,64
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blr
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/*
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* Vector add, floating point.
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*/
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_GLOBAL(vaddfp)
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mflr r12
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bl fpenable
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li r0,4
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mtctr r0
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li r6,0
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1: lfsx fr0,r4,r6
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lfsx fr1,r5,r6
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fadds fr0,fr0,fr1
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stfsx fr0,r3,r6
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addi r6,r6,4
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bdnz 1b
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b fpdisable
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/*
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* Vector subtract, floating point.
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*/
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_GLOBAL(vsubfp)
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mflr r12
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bl fpenable
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li r0,4
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mtctr r0
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li r6,0
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1: lfsx fr0,r4,r6
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lfsx fr1,r5,r6
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fsubs fr0,fr0,fr1
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stfsx fr0,r3,r6
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addi r6,r6,4
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bdnz 1b
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b fpdisable
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/*
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* Vector multiply and add, floating point.
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*/
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_GLOBAL(vmaddfp)
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mflr r12
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bl fpenable
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stfd fr2,32(r1)
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li r0,4
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mtctr r0
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li r7,0
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1: lfsx fr0,r4,r7
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lfsx fr1,r5,r7
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lfsx fr2,r6,r7
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fmadds fr0,fr0,fr2,fr1
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stfsx fr0,r3,r7
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addi r7,r7,4
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bdnz 1b
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lfd fr2,32(r1)
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b fpdisable
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/*
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* Vector negative multiply and subtract, floating point.
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*/
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_GLOBAL(vnmsubfp)
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mflr r12
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bl fpenable
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stfd fr2,32(r1)
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li r0,4
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mtctr r0
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li r7,0
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1: lfsx fr0,r4,r7
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lfsx fr1,r5,r7
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lfsx fr2,r6,r7
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fnmsubs fr0,fr0,fr2,fr1
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stfsx fr0,r3,r7
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addi r7,r7,4
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bdnz 1b
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lfd fr2,32(r1)
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b fpdisable
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/*
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* Vector reciprocal estimate. We just compute 1.0/x.
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* r3 -> destination, r4 -> source.
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*/
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_GLOBAL(vrefp)
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mflr r12
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bl fpenable
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li r0,4
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LDCONST(fr1, fpone)
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mtctr r0
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li r6,0
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1: lfsx fr0,r4,r6
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fdivs fr0,fr1,fr0
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stfsx fr0,r3,r6
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addi r6,r6,4
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bdnz 1b
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b fpdisable
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/*
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* Vector reciprocal square-root estimate, floating point.
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* We use the frsqrte instruction for the initial estimate followed
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* by 2 iterations of Newton-Raphson to get sufficient accuracy.
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* r3 -> destination, r4 -> source.
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*/
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_GLOBAL(vrsqrtefp)
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mflr r12
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bl fpenable
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stfd fr2,32(r1)
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stfd fr3,40(r1)
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stfd fr4,48(r1)
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stfd fr5,56(r1)
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li r0,4
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LDCONST(fr4, fpone)
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LDCONST(fr5, fphalf)
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mtctr r0
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li r6,0
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1: lfsx fr0,r4,r6
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frsqrte fr1,fr0 /* r = frsqrte(s) */
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fmuls fr3,fr1,fr0 /* r * s */
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fmuls fr2,fr1,fr5 /* r * 0.5 */
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fnmsubs fr3,fr1,fr3,fr4 /* 1 - s * r * r */
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fmadds fr1,fr2,fr3,fr1 /* r = r + 0.5 * r * (1 - s * r * r) */
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fmuls fr3,fr1,fr0 /* r * s */
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fmuls fr2,fr1,fr5 /* r * 0.5 */
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fnmsubs fr3,fr1,fr3,fr4 /* 1 - s * r * r */
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fmadds fr1,fr2,fr3,fr1 /* r = r + 0.5 * r * (1 - s * r * r) */
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stfsx fr1,r3,r6
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addi r6,r6,4
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bdnz 1b
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lfd fr5,56(r1)
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lfd fr4,48(r1)
|
|
lfd fr3,40(r1)
|
|
lfd fr2,32(r1)
|
|
b fpdisable
|