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c98f506287
For disabling L3 clock gating we need to set bit 25 of MMIO register 940c. Earlier this was being done by just writing 1 into bit 25 and resetting all other bits. This patch modifies the routine to read-modify-write of the register, so that the values of other bits are not destroyed. v2: Modifying the comments and the patch commit message (Chris) Signed-off-by: Akash Goel <akash.goel@intel.com> Signed-off-by: Sourab Gupta <sourab.gupta@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> [danvet: Apply checkpatch fixup.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
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