Paul Walmsley c9812d042a OMAP3 clock: add a short delay when lowering CORE clk rate ... When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2 divider, add a short delay before returning to SDRAM to allow the SDRC time to stabilize. Without this delay, the system is prone to random panics upon re-entering SDRAM. This time delay varies based on MPU frequency. At 500MHz MPU frequency at room temperature, 64 loops seems to work okay; so add another 32 loops for environmental and process variation. Signed-off-by: Paul Walmsley <paul@pwsan.com>		2009-06-19 19:09:31 -06:00
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mach	OMAP3 clock: add a short delay when lowering CORE clk rate	2009-06-19 19:09:31 -06:00