mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-12 01:16:45 +07:00
5a9a62bb03
When either rx_buf or tx_buf is not being used, i.e. for plain read- or write operations, the atmel_spi uses a fixed-size DMA buffer instead. If the transfer is longer than the size of this buffer, it is split into multiple DMA transfers. When the transfer is split like this, the atmel_spi driver ends up using the same DMA address again and again even for the buffer that came from the user, which is of course wrong. Fix this by adding the number of bytes already transferred to the DMA address so that the data ends up in the right place. Thanks to Wu Xuan for discovering this bug. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
678 lines
17 KiB
C
678 lines
17 KiB
C
/*
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* Driver for Atmel AT32 and AT91 SPI Controllers
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*
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* Copyright (C) 2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/spi/spi.h>
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#include <asm/io.h>
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#include <asm/arch/board.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/cpu.h>
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#include "atmel_spi.h"
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/*
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* The core SPI transfer engine just talks to a register bank to set up
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* DMA transfers; transfer queue progress is driven by IRQs. The clock
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* framework provides the base clock, subdivided for each spi_device.
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*
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* Newer controllers, marked with "new_1" flag, have:
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* - CR.LASTXFER
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* - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
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* - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
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* - SPI_CSRx.CSAAT
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* - SPI_CSRx.SBCR allows faster clocking
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*/
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struct atmel_spi {
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spinlock_t lock;
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void __iomem *regs;
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int irq;
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struct clk *clk;
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struct platform_device *pdev;
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unsigned new_1:1;
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u8 stopping;
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struct list_head queue;
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struct spi_transfer *current_transfer;
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unsigned long remaining_bytes;
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void *buffer;
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dma_addr_t buffer_dma;
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};
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#define BUFFER_SIZE PAGE_SIZE
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#define INVALID_DMA_ADDRESS 0xffffffff
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/*
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* Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
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* they assume that spi slave device state will not change on deselect, so
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* that automagic deselection is OK. Not so! Workaround uses nCSx pins
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* as GPIOs; or newer controllers have CSAAT and friends.
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*
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* Since the CSAAT functionality is a bit weird on newer controllers
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* as well, we use GPIO to control nCSx pins on all controllers.
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*/
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static inline void cs_activate(struct spi_device *spi)
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{
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unsigned gpio = (unsigned) spi->controller_data;
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unsigned active = spi->mode & SPI_CS_HIGH;
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dev_dbg(&spi->dev, "activate %u%s\n", gpio, active ? " (high)" : "");
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gpio_set_value(gpio, active);
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}
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static inline void cs_deactivate(struct spi_device *spi)
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{
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unsigned gpio = (unsigned) spi->controller_data;
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unsigned active = spi->mode & SPI_CS_HIGH;
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dev_dbg(&spi->dev, "DEactivate %u%s\n", gpio, active ? " (low)" : "");
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gpio_set_value(gpio, !active);
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}
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/*
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* Submit next transfer for DMA.
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* lock is held, spi irq is blocked
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*/
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static void atmel_spi_next_xfer(struct spi_master *master,
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struct spi_message *msg)
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{
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struct atmel_spi *as = spi_master_get_devdata(master);
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struct spi_transfer *xfer;
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u32 len;
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dma_addr_t tx_dma, rx_dma;
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xfer = as->current_transfer;
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if (!xfer || as->remaining_bytes == 0) {
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if (xfer)
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xfer = list_entry(xfer->transfer_list.next,
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struct spi_transfer, transfer_list);
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else
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xfer = list_entry(msg->transfers.next,
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struct spi_transfer, transfer_list);
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as->remaining_bytes = xfer->len;
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as->current_transfer = xfer;
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}
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len = as->remaining_bytes;
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tx_dma = xfer->tx_dma + xfer->len - len;
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rx_dma = xfer->rx_dma + xfer->len - len;
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/* use scratch buffer only when rx or tx data is unspecified */
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if (!xfer->rx_buf) {
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rx_dma = as->buffer_dma;
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if (len > BUFFER_SIZE)
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len = BUFFER_SIZE;
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}
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if (!xfer->tx_buf) {
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tx_dma = as->buffer_dma;
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if (len > BUFFER_SIZE)
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len = BUFFER_SIZE;
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memset(as->buffer, 0, len);
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dma_sync_single_for_device(&as->pdev->dev,
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as->buffer_dma, len, DMA_TO_DEVICE);
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}
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spi_writel(as, RPR, rx_dma);
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spi_writel(as, TPR, tx_dma);
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as->remaining_bytes -= len;
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if (msg->spi->bits_per_word > 8)
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len >>= 1;
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/* REVISIT: when xfer->delay_usecs == 0, the PDC "next transfer"
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* mechanism might help avoid the IRQ latency between transfers
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*
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* We're also waiting for ENDRX before we start the next
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* transfer because we need to handle some difficult timing
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* issues otherwise. If we wait for ENDTX in one transfer and
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* then starts waiting for ENDRX in the next, it's difficult
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* to tell the difference between the ENDRX interrupt we're
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* actually waiting for and the ENDRX interrupt of the
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* previous transfer.
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*
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* It should be doable, though. Just not now...
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*/
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spi_writel(as, TNCR, 0);
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spi_writel(as, RNCR, 0);
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spi_writel(as, IER, SPI_BIT(ENDRX) | SPI_BIT(OVRES));
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dev_dbg(&msg->spi->dev,
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" start xfer %p: len %u tx %p/%08x rx %p/%08x imr %03x\n",
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xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
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xfer->rx_buf, xfer->rx_dma, spi_readl(as, IMR));
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spi_writel(as, TCR, len);
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spi_writel(as, RCR, len);
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spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
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}
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static void atmel_spi_next_message(struct spi_master *master)
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{
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struct atmel_spi *as = spi_master_get_devdata(master);
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struct spi_message *msg;
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u32 mr;
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BUG_ON(as->current_transfer);
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msg = list_entry(as->queue.next, struct spi_message, queue);
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/* Select the chip */
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mr = spi_readl(as, MR);
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mr = SPI_BFINS(PCS, ~(1 << msg->spi->chip_select), mr);
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spi_writel(as, MR, mr);
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cs_activate(msg->spi);
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atmel_spi_next_xfer(master, msg);
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}
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static void
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atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
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{
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xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
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if (xfer->tx_buf)
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xfer->tx_dma = dma_map_single(&as->pdev->dev,
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(void *) xfer->tx_buf, xfer->len,
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DMA_TO_DEVICE);
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if (xfer->rx_buf)
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xfer->rx_dma = dma_map_single(&as->pdev->dev,
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xfer->rx_buf, xfer->len,
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DMA_FROM_DEVICE);
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}
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static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
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struct spi_transfer *xfer)
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{
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if (xfer->tx_dma != INVALID_DMA_ADDRESS)
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dma_unmap_single(master->cdev.dev, xfer->tx_dma,
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xfer->len, DMA_TO_DEVICE);
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if (xfer->rx_dma != INVALID_DMA_ADDRESS)
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dma_unmap_single(master->cdev.dev, xfer->rx_dma,
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xfer->len, DMA_FROM_DEVICE);
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}
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static void
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atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
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struct spi_message *msg, int status)
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{
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cs_deactivate(msg->spi);
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list_del(&msg->queue);
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msg->status = status;
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dev_dbg(master->cdev.dev,
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"xfer complete: %u bytes transferred\n",
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msg->actual_length);
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spin_unlock(&as->lock);
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msg->complete(msg->context);
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spin_lock(&as->lock);
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as->current_transfer = NULL;
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/* continue if needed */
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if (list_empty(&as->queue) || as->stopping)
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spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
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else
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atmel_spi_next_message(master);
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}
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static irqreturn_t
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atmel_spi_interrupt(int irq, void *dev_id)
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{
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struct spi_master *master = dev_id;
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struct atmel_spi *as = spi_master_get_devdata(master);
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struct spi_message *msg;
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struct spi_transfer *xfer;
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u32 status, pending, imr;
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int ret = IRQ_NONE;
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spin_lock(&as->lock);
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xfer = as->current_transfer;
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msg = list_entry(as->queue.next, struct spi_message, queue);
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imr = spi_readl(as, IMR);
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status = spi_readl(as, SR);
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pending = status & imr;
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if (pending & SPI_BIT(OVRES)) {
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int timeout;
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ret = IRQ_HANDLED;
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spi_writel(as, IDR, (SPI_BIT(ENDTX) | SPI_BIT(ENDRX)
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| SPI_BIT(OVRES)));
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/*
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* When we get an overrun, we disregard the current
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* transfer. Data will not be copied back from any
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* bounce buffer and msg->actual_len will not be
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* updated with the last xfer.
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*
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* We will also not process any remaning transfers in
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* the message.
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*
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* First, stop the transfer and unmap the DMA buffers.
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*/
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spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
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if (!msg->is_dma_mapped)
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atmel_spi_dma_unmap_xfer(master, xfer);
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/* REVISIT: udelay in irq is unfriendly */
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if (xfer->delay_usecs)
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udelay(xfer->delay_usecs);
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dev_warn(master->cdev.dev, "fifo overrun (%u/%u remaining)\n",
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spi_readl(as, TCR), spi_readl(as, RCR));
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/*
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* Clean up DMA registers and make sure the data
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* registers are empty.
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*/
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spi_writel(as, RNCR, 0);
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spi_writel(as, TNCR, 0);
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spi_writel(as, RCR, 0);
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spi_writel(as, TCR, 0);
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for (timeout = 1000; timeout; timeout--)
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if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
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break;
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if (!timeout)
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dev_warn(master->cdev.dev,
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"timeout waiting for TXEMPTY");
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while (spi_readl(as, SR) & SPI_BIT(RDRF))
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spi_readl(as, RDR);
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/* Clear any overrun happening while cleaning up */
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spi_readl(as, SR);
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atmel_spi_msg_done(master, as, msg, -EIO);
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} else if (pending & SPI_BIT(ENDRX)) {
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ret = IRQ_HANDLED;
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spi_writel(as, IDR, pending);
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if (as->remaining_bytes == 0) {
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msg->actual_length += xfer->len;
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if (!msg->is_dma_mapped)
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atmel_spi_dma_unmap_xfer(master, xfer);
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/* REVISIT: udelay in irq is unfriendly */
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if (xfer->delay_usecs)
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udelay(xfer->delay_usecs);
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if (msg->transfers.prev == &xfer->transfer_list) {
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/* report completed message */
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atmel_spi_msg_done(master, as, msg, 0);
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} else {
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if (xfer->cs_change) {
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cs_deactivate(msg->spi);
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udelay(1);
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cs_activate(msg->spi);
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}
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/*
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* Not done yet. Submit the next transfer.
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*
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* FIXME handle protocol options for xfer
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*/
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atmel_spi_next_xfer(master, msg);
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}
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} else {
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/*
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* Keep going, we still have data to send in
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* the current transfer.
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*/
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atmel_spi_next_xfer(master, msg);
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}
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}
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spin_unlock(&as->lock);
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return ret;
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}
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#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
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static int atmel_spi_setup(struct spi_device *spi)
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{
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struct atmel_spi *as;
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u32 scbr, csr;
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unsigned int bits = spi->bits_per_word;
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unsigned long bus_hz, sck_hz;
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unsigned int npcs_pin;
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int ret;
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as = spi_master_get_devdata(spi->master);
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if (as->stopping)
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return -ESHUTDOWN;
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if (spi->chip_select > spi->master->num_chipselect) {
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dev_dbg(&spi->dev,
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"setup: invalid chipselect %u (%u defined)\n",
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spi->chip_select, spi->master->num_chipselect);
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return -EINVAL;
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}
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if (bits == 0)
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bits = 8;
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if (bits < 8 || bits > 16) {
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dev_dbg(&spi->dev,
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"setup: invalid bits_per_word %u (8 to 16)\n",
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bits);
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return -EINVAL;
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}
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if (spi->mode & ~MODEBITS) {
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dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
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spi->mode & ~MODEBITS);
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return -EINVAL;
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}
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/* speed zero convention is used by some upper layers */
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bus_hz = clk_get_rate(as->clk);
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if (spi->max_speed_hz) {
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/* assume div32/fdiv/mbz == 0 */
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if (!as->new_1)
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bus_hz /= 2;
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scbr = ((bus_hz + spi->max_speed_hz - 1)
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/ spi->max_speed_hz);
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if (scbr >= (1 << SPI_SCBR_SIZE)) {
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dev_dbg(&spi->dev, "setup: %d Hz too slow, scbr %u\n",
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spi->max_speed_hz, scbr);
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return -EINVAL;
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}
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} else
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scbr = 0xff;
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sck_hz = bus_hz / scbr;
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csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
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if (spi->mode & SPI_CPOL)
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csr |= SPI_BIT(CPOL);
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if (!(spi->mode & SPI_CPHA))
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csr |= SPI_BIT(NCPHA);
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/* TODO: DLYBS and DLYBCT */
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csr |= SPI_BF(DLYBS, 10);
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csr |= SPI_BF(DLYBCT, 10);
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/* chipselect must have been muxed as GPIO (e.g. in board setup) */
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npcs_pin = (unsigned int)spi->controller_data;
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if (!spi->controller_state) {
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ret = gpio_request(npcs_pin, "spi_npcs");
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if (ret)
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return ret;
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spi->controller_state = (void *)npcs_pin;
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gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
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}
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dev_dbg(&spi->dev,
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"setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
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sck_hz, bits, spi->mode, spi->chip_select, csr);
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spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
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return 0;
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}
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static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
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{
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struct atmel_spi *as;
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struct spi_transfer *xfer;
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unsigned long flags;
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struct device *controller = spi->master->cdev.dev;
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as = spi_master_get_devdata(spi->master);
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dev_dbg(controller, "new message %p submitted for %s\n",
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msg, spi->dev.bus_id);
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if (unlikely(list_empty(&msg->transfers)
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|| !spi->max_speed_hz))
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return -EINVAL;
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if (as->stopping)
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return -ESHUTDOWN;
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list_for_each_entry(xfer, &msg->transfers, transfer_list) {
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if (!(xfer->tx_buf || xfer->rx_buf)) {
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dev_dbg(&spi->dev, "missing rx or tx buf\n");
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return -EINVAL;
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}
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/* FIXME implement these protocol options!! */
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if (xfer->bits_per_word || xfer->speed_hz) {
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dev_dbg(&spi->dev, "no protocol options yet\n");
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return -ENOPROTOOPT;
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}
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}
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/* scrub dcache "early" */
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if (!msg->is_dma_mapped) {
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list_for_each_entry(xfer, &msg->transfers, transfer_list)
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atmel_spi_dma_map_xfer(as, xfer);
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}
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list_for_each_entry(xfer, &msg->transfers, transfer_list) {
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dev_dbg(controller,
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" xfer %p: len %u tx %p/%08x rx %p/%08x\n",
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xfer, xfer->len,
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xfer->tx_buf, xfer->tx_dma,
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xfer->rx_buf, xfer->rx_dma);
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}
|
|
|
|
msg->status = -EINPROGRESS;
|
|
msg->actual_length = 0;
|
|
|
|
spin_lock_irqsave(&as->lock, flags);
|
|
list_add_tail(&msg->queue, &as->queue);
|
|
if (!as->current_transfer)
|
|
atmel_spi_next_message(spi->master);
|
|
spin_unlock_irqrestore(&as->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void atmel_spi_cleanup(struct spi_device *spi)
|
|
{
|
|
if (spi->controller_state)
|
|
gpio_free((unsigned int)spi->controller_data);
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
static int __init atmel_spi_probe(struct platform_device *pdev)
|
|
{
|
|
struct resource *regs;
|
|
int irq;
|
|
struct clk *clk;
|
|
int ret;
|
|
struct spi_master *master;
|
|
struct atmel_spi *as;
|
|
|
|
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!regs)
|
|
return -ENXIO;
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0)
|
|
return irq;
|
|
|
|
clk = clk_get(&pdev->dev, "spi_clk");
|
|
if (IS_ERR(clk))
|
|
return PTR_ERR(clk);
|
|
|
|
/* setup spi core then atmel-specific driver state */
|
|
ret = -ENOMEM;
|
|
master = spi_alloc_master(&pdev->dev, sizeof *as);
|
|
if (!master)
|
|
goto out_free;
|
|
|
|
master->bus_num = pdev->id;
|
|
master->num_chipselect = 4;
|
|
master->setup = atmel_spi_setup;
|
|
master->transfer = atmel_spi_transfer;
|
|
master->cleanup = atmel_spi_cleanup;
|
|
platform_set_drvdata(pdev, master);
|
|
|
|
as = spi_master_get_devdata(master);
|
|
|
|
as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
|
|
&as->buffer_dma, GFP_KERNEL);
|
|
if (!as->buffer)
|
|
goto out_free;
|
|
|
|
spin_lock_init(&as->lock);
|
|
INIT_LIST_HEAD(&as->queue);
|
|
as->pdev = pdev;
|
|
as->regs = ioremap(regs->start, (regs->end - regs->start) + 1);
|
|
if (!as->regs)
|
|
goto out_free_buffer;
|
|
as->irq = irq;
|
|
as->clk = clk;
|
|
if (!cpu_is_at91rm9200())
|
|
as->new_1 = 1;
|
|
|
|
ret = request_irq(irq, atmel_spi_interrupt, 0,
|
|
pdev->dev.bus_id, master);
|
|
if (ret)
|
|
goto out_unmap_regs;
|
|
|
|
/* Initialize the hardware */
|
|
clk_enable(clk);
|
|
spi_writel(as, CR, SPI_BIT(SWRST));
|
|
spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
|
|
spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
|
|
spi_writel(as, CR, SPI_BIT(SPIEN));
|
|
|
|
/* go! */
|
|
dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
|
|
(unsigned long)regs->start, irq);
|
|
|
|
ret = spi_register_master(master);
|
|
if (ret)
|
|
goto out_reset_hw;
|
|
|
|
return 0;
|
|
|
|
out_reset_hw:
|
|
spi_writel(as, CR, SPI_BIT(SWRST));
|
|
clk_disable(clk);
|
|
free_irq(irq, master);
|
|
out_unmap_regs:
|
|
iounmap(as->regs);
|
|
out_free_buffer:
|
|
dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
|
|
as->buffer_dma);
|
|
out_free:
|
|
clk_put(clk);
|
|
spi_master_put(master);
|
|
return ret;
|
|
}
|
|
|
|
static int __exit atmel_spi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
struct atmel_spi *as = spi_master_get_devdata(master);
|
|
struct spi_message *msg;
|
|
|
|
/* reset the hardware and block queue progress */
|
|
spin_lock_irq(&as->lock);
|
|
as->stopping = 1;
|
|
spi_writel(as, CR, SPI_BIT(SWRST));
|
|
spi_readl(as, SR);
|
|
spin_unlock_irq(&as->lock);
|
|
|
|
/* Terminate remaining queued transfers */
|
|
list_for_each_entry(msg, &as->queue, queue) {
|
|
/* REVISIT unmapping the dma is a NOP on ARM and AVR32
|
|
* but we shouldn't depend on that...
|
|
*/
|
|
msg->status = -ESHUTDOWN;
|
|
msg->complete(msg->context);
|
|
}
|
|
|
|
dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
|
|
as->buffer_dma);
|
|
|
|
clk_disable(as->clk);
|
|
clk_put(as->clk);
|
|
free_irq(as->irq, master);
|
|
iounmap(as->regs);
|
|
|
|
spi_unregister_master(master);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
struct atmel_spi *as = spi_master_get_devdata(master);
|
|
|
|
clk_disable(as->clk);
|
|
return 0;
|
|
}
|
|
|
|
static int atmel_spi_resume(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master = platform_get_drvdata(pdev);
|
|
struct atmel_spi *as = spi_master_get_devdata(master);
|
|
|
|
clk_enable(as->clk);
|
|
return 0;
|
|
}
|
|
|
|
#else
|
|
#define atmel_spi_suspend NULL
|
|
#define atmel_spi_resume NULL
|
|
#endif
|
|
|
|
|
|
static struct platform_driver atmel_spi_driver = {
|
|
.driver = {
|
|
.name = "atmel_spi",
|
|
.owner = THIS_MODULE,
|
|
},
|
|
.suspend = atmel_spi_suspend,
|
|
.resume = atmel_spi_resume,
|
|
.remove = __exit_p(atmel_spi_remove),
|
|
};
|
|
|
|
static int __init atmel_spi_init(void)
|
|
{
|
|
return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
|
|
}
|
|
module_init(atmel_spi_init);
|
|
|
|
static void __exit atmel_spi_exit(void)
|
|
{
|
|
platform_driver_unregister(&atmel_spi_driver);
|
|
}
|
|
module_exit(atmel_spi_exit);
|
|
|
|
MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
|
|
MODULE_AUTHOR("Haavard Skinnemoen <hskinnemoen@atmel.com>");
|
|
MODULE_LICENSE("GPL");
|