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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e269a86941
That simulator is dead and redundant. Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
268 lines
8.1 KiB
C
268 lines
8.1 KiB
C
/*
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* linux/arch/cris/arch-v10/kernel/time.c
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*
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* Copyright (C) 1991, 1992, 1995 Linus Torvalds
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* Copyright (C) 1999-2002 Axis Communications AB
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*
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*/
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#include <linux/timex.h>
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#include <linux/time.h>
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#include <linux/jiffies.h>
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#include <linux/interrupt.h>
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#include <linux/swap.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <asm/types.h>
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#include <asm/signal.h>
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#include <asm/io.h>
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#include <asm/delay.h>
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#include <asm/irq_regs.h>
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/* define this if you need to use print_timestamp */
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/* it will make jiffies at 96 hz instead of 100 hz though */
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#undef USE_CASCADE_TIMERS
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unsigned long get_ns_in_jiffie(void)
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{
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unsigned char timer_count, t1;
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unsigned short presc_count;
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unsigned long ns;
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unsigned long flags;
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local_irq_save(flags);
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timer_count = *R_TIMER0_DATA;
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presc_count = *R_TIM_PRESC_STATUS;
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/* presc_count might be wrapped */
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t1 = *R_TIMER0_DATA;
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if (timer_count != t1){
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/* it wrapped, read prescaler again... */
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presc_count = *R_TIM_PRESC_STATUS;
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timer_count = t1;
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}
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local_irq_restore(flags);
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if (presc_count >= PRESCALE_VALUE/2 ){
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presc_count = PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
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} else {
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presc_count = PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
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}
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ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) +
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( (presc_count) * (1000000000/PRESCALE_FREQ));
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return ns;
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}
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static u32 cris_v10_gettimeoffset(void)
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{
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u32 count;
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/* The timer interrupt comes from Etrax timer 0. In order to get
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* better precision, we check the current value. It might have
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* underflowed already though.
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*/
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count = *R_TIMER0_DATA;
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/* Convert timer value to nsec */
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return (TIMER0_DIV - count) * (NSEC_PER_SEC/HZ)/TIMER0_DIV;
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}
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/* Excerpt from the Etrax100 HSDD about the built-in watchdog:
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*
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* 3.10.4 Watchdog timer
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* When the watchdog timer is started, it generates an NMI if the watchdog
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* isn't restarted or stopped within 0.1 s. If it still isn't restarted or
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* stopped after an additional 3.3 ms, the watchdog resets the chip.
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* The watchdog timer is stopped after reset. The watchdog timer is controlled
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* by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
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* and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
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* described in the table below:
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*
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* Watchdog Value written:
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* state: To enable: To key: Operation:
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* -------- ---------- ------- ----------
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* stopped 0 X No effect.
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* stopped 1 key_val Start watchdog with key = key_val.
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* started 0 ~key Stop watchdog
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* started 1 ~key Restart watchdog with key = ~key.
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* started X new_key_val Change key to new_key_val.
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*
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* Note: '~' is the bitwise NOT operator.
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*
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*/
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/* right now, starting the watchdog is the same as resetting it */
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#define start_watchdog reset_watchdog
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#ifdef CONFIG_ETRAX_WATCHDOG
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static int watchdog_key = 0; /* arbitrary number */
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#endif
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/* number of pages to consider "out of memory". it is normal that the memory
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* is used though, so put this really low.
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*/
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#define WATCHDOG_MIN_FREE_PAGES 8
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void reset_watchdog(void)
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{
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#if defined(CONFIG_ETRAX_WATCHDOG)
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/* only keep watchdog happy as long as we have memory left! */
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if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
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/* reset the watchdog with the inverse of the old key */
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watchdog_key ^= 0x7; /* invert key, which is 3 bits */
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*R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
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IO_STATE(R_WATCHDOG, enable, start);
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}
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#endif
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}
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/* stop the watchdog - we still need the correct key */
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void stop_watchdog(void)
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{
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#ifdef CONFIG_ETRAX_WATCHDOG
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watchdog_key ^= 0x7; /* invert key, which is 3 bits */
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*R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
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IO_STATE(R_WATCHDOG, enable, stop);
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#endif
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}
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extern void cris_do_profile(struct pt_regs *regs);
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/*
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* timer_interrupt() needs to keep up the real-time clock,
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* as well as call the "xtime_update()" routine every clocktick
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*/
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static inline irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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struct pt_regs *regs = get_irq_regs();
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/* acknowledge the timer irq */
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#ifdef USE_CASCADE_TIMERS
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*R_TIMER_CTRL =
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IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
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IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
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IO_STATE( R_TIMER_CTRL, i1, clr) |
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IO_STATE( R_TIMER_CTRL, tm1, run) |
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IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
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IO_STATE( R_TIMER_CTRL, i0, clr) |
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IO_STATE( R_TIMER_CTRL, tm0, run) |
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IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
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#else
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*R_TIMER_CTRL = r_timer_ctrl_shadow | IO_STATE(R_TIMER_CTRL, i0, clr);
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#endif
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/* reset watchdog otherwise it resets us! */
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reset_watchdog();
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/* Update statistics. */
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update_process_times(user_mode(regs));
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/* call the real timer interrupt handler */
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xtime_update(1);
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cris_do_profile(regs); /* Save profiling information */
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return IRQ_HANDLED;
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}
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/* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain */
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static struct irqaction irq2 = {
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.handler = timer_interrupt,
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.flags = IRQF_SHARED,
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.name = "timer",
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};
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void __init time_init(void)
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{
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arch_gettimeoffset = cris_v10_gettimeoffset;
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/* probe for the RTC and read it if it exists
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* Before the RTC can be probed the loops_per_usec variable needs
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* to be initialized to make usleep work. A better value for
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* loops_per_usec is calculated by the kernel later once the
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* clock has started.
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*/
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loops_per_usec = 50;
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/* Setup the etrax timers
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* Base frequency is 25000 hz, divider 250 -> 100 HZ
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* In normal mode, we use timer0, so timer1 is free. In cascade
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* mode (which we sometimes use for debugging) both timers are used.
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* Remember that linux/timex.h contains #defines that rely on the
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* timer settings below (hz and divide factor) !!!
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*/
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#ifdef USE_CASCADE_TIMERS
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*R_TIMER_CTRL =
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IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
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IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
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IO_STATE( R_TIMER_CTRL, i1, nop) |
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IO_STATE( R_TIMER_CTRL, tm1, stop_ld) |
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IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
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IO_STATE( R_TIMER_CTRL, i0, nop) |
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IO_STATE( R_TIMER_CTRL, tm0, stop_ld) |
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IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
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*R_TIMER_CTRL = r_timer_ctrl_shadow =
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IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
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IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
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IO_STATE( R_TIMER_CTRL, i1, nop) |
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IO_STATE( R_TIMER_CTRL, tm1, run) |
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IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
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IO_STATE( R_TIMER_CTRL, i0, nop) |
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IO_STATE( R_TIMER_CTRL, tm0, run) |
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IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
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#else
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*R_TIMER_CTRL =
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IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) |
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IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) |
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IO_STATE(R_TIMER_CTRL, i1, nop) |
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IO_STATE(R_TIMER_CTRL, tm1, stop_ld) |
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IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) |
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IO_STATE(R_TIMER_CTRL, i0, nop) |
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IO_STATE(R_TIMER_CTRL, tm0, stop_ld) |
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IO_STATE(R_TIMER_CTRL, clksel0, flexible);
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*R_TIMER_CTRL = r_timer_ctrl_shadow =
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IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) |
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IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) |
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IO_STATE(R_TIMER_CTRL, i1, nop) |
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IO_STATE(R_TIMER_CTRL, tm1, run) |
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IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) |
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IO_STATE(R_TIMER_CTRL, i0, nop) |
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IO_STATE(R_TIMER_CTRL, tm0, run) |
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IO_STATE(R_TIMER_CTRL, clksel0, flexible);
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*R_TIMER_PRESCALE = PRESCALE_VALUE;
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#endif
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/* unmask the timer irq */
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*R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, timer0, set);
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/* now actually register the irq handler that calls timer_interrupt() */
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setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */
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/* enable watchdog if we should use one */
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#if defined(CONFIG_ETRAX_WATCHDOG)
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printk("Enabling watchdog...\n");
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start_watchdog();
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/* If we use the hardware watchdog, we want to trap it as an NMI
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and dump registers before it resets us. For this to happen, we
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must set the "m" NMI enable flag (which once set, is unset only
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when an NMI is taken).
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The same goes for the external NMI, but that doesn't have any
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driver or infrastructure support yet. */
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asm ("setf m");
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*R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
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*R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, nmi, set);
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#endif
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}
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