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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a6ed68d646
-----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJd3YntAAoJEAx081l5xIa+dcQP/ikABkpm+q23FLKteRpL1rtX xqlg5+KHW+YVCDls2BrINF6vYzyisoa8fNPlKMmOHse/IgMhFe9vBbCj1KQQOUR1 apNycI1wrcw/mn2WDikoIcF6C5cjqK9YVknnYoM6HnF1VmpGd1ecSGrOHrunEkrK cMAWYIeqWGU8Gj/HUOitAFpLWFUMNle0BJuRoGLcoMusgS8yuCIEcpNzRhgL8fvJ bW4imuyv24OjPoQzbKD0oQ0VIP86H0eM4LIeGZ2uyK/BSPKmMDqI4z4isUheS7RL w4a6BdobMIdhew5dBXS0LsUJ3JniVJdHy123q9KgpmQAhGpiNoLT6BujfoUTUeWx Mu0vM8Xmv9n4npdBYC+fLEFQXYJlu9uBA490jP84Kz6Fg1c6GyBebDY7/c2O4Zmg 7pvygmUF6boD6v2sIC/3161crgwU4g8zoxm2V4i9naxes2QB13LiEuJWlaI/FdxY fd3zpglFGdoF1ThNne4QDh6gMKpXvjITyu/QxZeZ67Dt6i0Aqw9cRGHSpiVhYyDc cx2hAp+rDvUi5SHkJKFpVImjB2DDn2xUG2uFMHz0cy9wNg203L3fRDi0hVtnM1+W VpCxyLs2Upz6kEjDRVsfMZ9chCcWAWpVuKhtuuMUDw/IKnbP3uV8kzgJpVpaRVkD 76s5uYWHHBlk1IVlkOUP =Hj7G -----END PGP SIGNATURE----- Merge tag 'drm-next-2019-11-27' of git://anongit.freedesktop.org/drm/drm Pull drm updates from Dave Airlie: "Lots of stuff in here, though it hasn't been too insane this merge apart from dealing with the security fun. uapi: - export different colorspace properties on DP vs HDMI - new fourcc for ARM 16x16 block format - syncobj: allow querying last submitted timeline value - DRM_FORMAT_BIG_ENDIAN defined as unsigned core: - allow using gem vma manager in ttm - connector/encoder/bridge doc fixes - allow more than 3 encoders for a connector - displayport mst suspend/resume reprobing support - vram lazy unmapping, uniform vram mm and gem vram - edid cleanups + AVI informframe bar info - displayport helpers - dpcd parser added dp_cec: - Allow a connector to be associated with a cec device ttm: - pipelining with no_gpu_wait fix - always keep BOs on the LRU sched: - allow free_job routine to sleep i915: - Block userptr from mappable GTT - i915 perf uapi versioning - OA stream dynamic reconfiguration - make context persistence optional - introduce DRM_I915_UNSTABLE Kconfig - add fake lmem testing under unstable - BT.2020 support for DP MSA - struct mutex elimination - Tigerlake display/PLL/power management improvements - Jasper Lake PCH support - refactor PMU for multiple GPUs - Icelake firmware update - Split out vga + switcheroo code amdgpu: - implement dma-buf import/export without helpers - vega20 RAS enablement - DC i2c over aux fixes - renoir GPU reset - DC HDCP support - BACO support for CI/VI asics - MSI-X support - Arcturus EEPROM support - Arcturus VCN encode support - VCN dynamic powergating on RV/RV2 amdkfd: - add navi12/14/renoir support to kfd radeon: - SI dpm fix ported from amdgpu - fix bad DMA on ppc platforms gma500: - memory leak fixes qxl: - convert to new gem mmap exynos: - build warning fix komeda: - add aclk sysfs attribute v3d: - userspace cleanup uapi change i810: - fix for underflow in dispatch ioctls ast: - refactor show_cursor mgag200: - refactor show_cursor arcgpu: - encoder finding improvements mediatek: - mipi_tx, dsi and partial crtc support for MT8183 SoC - rotation support meson: - add suspend/resume support omap: - misc refactors tegra: - DisplayPort support for Tegra 210, 186 and 194. - IOMMU-backed DMA API fixes panfrost: - fix lockdep issue - simplify devfreq integration rcar-du: - R8A774B1 SoC support - fixes for H2 ES2.0 sun4i: - vcc-dsi regulator support virtio-gpu: - vmexit vs spinlock fix - move to gem shmem helpers - handle large command buffers with cma" * tag 'drm-next-2019-11-27' of git://anongit.freedesktop.org/drm/drm: (1855 commits) drm/amdgpu: invalidate mmhub semaphore workaround in gmc9/gmc10 drm/amdgpu: initialize vm_inv_eng0_sem for gfxhub and mmhub drm/amd/amdgpu/sriov skip RLCG s/r list for arcturus VF. drm/amd/amdgpu/sriov temporarily skip ras,dtm,hdcp for arcturus VF drm/amdgpu/gfx10: re-init clear state buffer after gpu reset merge fix for "ftrace: Rework event_create_dir()" drm/amdgpu: Update Arcturus golden registers drm/amdgpu/gfx10: fix out-of-bound mqd_backup array access drm/amdgpu/gfx10: explicitly wait for cp idle after halt/unhalt Revert "drm/amd/display: enable S/G for RAVEN chip" drm/amdgpu: disable gfxoff on original raven drm/amdgpu: remove experimental flag for Navi14 drm/amdgpu: disable gfxoff when using register read interface drm/amdgpu/powerplay: properly set PP_GFXOFF_MASK (v2) drm/amdgpu: fix bad DMA from INTERRUPT_CNTL2 drm/radeon: fix bad DMA from INTERRUPT_CNTL2 drm/amd/display: Fix debugfs on MST connectors drm/amdgpu/nv: add asic func for fetching vbios from rom directly drm/amdgpu: put flush_delayed_work at first drm/amdgpu/vcn2.5: fix the enc loop with hw fini ...
186 lines
8.8 KiB
C
186 lines
8.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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*/
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#ifndef __DW_HDMI__
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#define __DW_HDMI__
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#include <sound/hdmi-codec.h>
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struct drm_connector;
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struct drm_display_mode;
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struct drm_encoder;
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struct dw_hdmi;
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struct platform_device;
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/**
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* DOC: Supported input formats and encodings
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*
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* Depending on the Hardware configuration of the Controller IP, it supports
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* a subset of the following input formats and encodings on its internal
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* 48bit bus.
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*
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* +----------------------+----------------------------------+------------------------------+
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* | Format Name | Format Code | Encodings |
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* +----------------------+----------------------------------+------------------------------+
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* | RGB 4:4:4 8bit | ``MEDIA_BUS_FMT_RGB888_1X24`` | ``V4L2_YCBCR_ENC_DEFAULT`` |
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* +----------------------+----------------------------------+------------------------------+
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* | RGB 4:4:4 10bits | ``MEDIA_BUS_FMT_RGB101010_1X30`` | ``V4L2_YCBCR_ENC_DEFAULT`` |
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* +----------------------+----------------------------------+------------------------------+
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* | RGB 4:4:4 12bits | ``MEDIA_BUS_FMT_RGB121212_1X36`` | ``V4L2_YCBCR_ENC_DEFAULT`` |
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* +----------------------+----------------------------------+------------------------------+
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* | RGB 4:4:4 16bits | ``MEDIA_BUS_FMT_RGB161616_1X48`` | ``V4L2_YCBCR_ENC_DEFAULT`` |
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* +----------------------+----------------------------------+------------------------------+
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* | YCbCr 4:4:4 8bit | ``MEDIA_BUS_FMT_YUV8_1X24`` | ``V4L2_YCBCR_ENC_601`` |
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* | | | or ``V4L2_YCBCR_ENC_709`` |
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* | | | or ``V4L2_YCBCR_ENC_XV601`` |
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* | | | or ``V4L2_YCBCR_ENC_XV709`` |
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* +----------------------+----------------------------------+------------------------------+
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* | YCbCr 4:4:4 10bits | ``MEDIA_BUS_FMT_YUV10_1X30`` | ``V4L2_YCBCR_ENC_601`` |
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* | | | or ``V4L2_YCBCR_ENC_709`` |
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* | | | or ``V4L2_YCBCR_ENC_XV601`` |
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* | | | or ``V4L2_YCBCR_ENC_XV709`` |
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* +----------------------+----------------------------------+------------------------------+
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* | YCbCr 4:4:4 12bits | ``MEDIA_BUS_FMT_YUV12_1X36`` | ``V4L2_YCBCR_ENC_601`` |
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* | | | or ``V4L2_YCBCR_ENC_709`` |
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* | | | or ``V4L2_YCBCR_ENC_XV601`` |
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* | | | or ``V4L2_YCBCR_ENC_XV709`` |
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* +----------------------+----------------------------------+------------------------------+
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* | YCbCr 4:4:4 16bits | ``MEDIA_BUS_FMT_YUV16_1X48`` | ``V4L2_YCBCR_ENC_601`` |
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* | | | or ``V4L2_YCBCR_ENC_709`` |
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* | | | or ``V4L2_YCBCR_ENC_XV601`` |
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* | | | or ``V4L2_YCBCR_ENC_XV709`` |
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* +----------------------+----------------------------------+------------------------------+
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* | YCbCr 4:2:2 8bit | ``MEDIA_BUS_FMT_UYVY8_1X16`` | ``V4L2_YCBCR_ENC_601`` |
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* | | | or ``V4L2_YCBCR_ENC_709`` |
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* +----------------------+----------------------------------+------------------------------+
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* | YCbCr 4:2:2 10bits | ``MEDIA_BUS_FMT_UYVY10_1X20`` | ``V4L2_YCBCR_ENC_601`` |
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* | | | or ``V4L2_YCBCR_ENC_709`` |
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* +----------------------+----------------------------------+------------------------------+
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* | YCbCr 4:2:2 12bits | ``MEDIA_BUS_FMT_UYVY12_1X24`` | ``V4L2_YCBCR_ENC_601`` |
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* | | | or ``V4L2_YCBCR_ENC_709`` |
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* +----------------------+----------------------------------+------------------------------+
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* | YCbCr 4:2:0 8bit | ``MEDIA_BUS_FMT_UYYVYY8_0_5X24`` | ``V4L2_YCBCR_ENC_601`` |
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* | | | or ``V4L2_YCBCR_ENC_709`` |
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* +----------------------+----------------------------------+------------------------------+
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* | YCbCr 4:2:0 10bits | ``MEDIA_BUS_FMT_UYYVYY10_0_5X30``| ``V4L2_YCBCR_ENC_601`` |
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* | | | or ``V4L2_YCBCR_ENC_709`` |
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* +----------------------+----------------------------------+------------------------------+
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* | YCbCr 4:2:0 12bits | ``MEDIA_BUS_FMT_UYYVYY12_0_5X36``| ``V4L2_YCBCR_ENC_601`` |
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* | | | or ``V4L2_YCBCR_ENC_709`` |
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* +----------------------+----------------------------------+------------------------------+
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* | YCbCr 4:2:0 16bits | ``MEDIA_BUS_FMT_UYYVYY16_0_5X48``| ``V4L2_YCBCR_ENC_601`` |
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* | | | or ``V4L2_YCBCR_ENC_709`` |
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* +----------------------+----------------------------------+------------------------------+
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*/
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enum {
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DW_HDMI_RES_8,
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DW_HDMI_RES_10,
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DW_HDMI_RES_12,
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DW_HDMI_RES_MAX,
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};
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enum dw_hdmi_phy_type {
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DW_HDMI_PHY_DWC_HDMI_TX_PHY = 0x00,
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DW_HDMI_PHY_DWC_MHL_PHY_HEAC = 0xb2,
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DW_HDMI_PHY_DWC_MHL_PHY = 0xc2,
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DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC = 0xe2,
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DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY = 0xf2,
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DW_HDMI_PHY_DWC_HDMI20_TX_PHY = 0xf3,
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DW_HDMI_PHY_VENDOR_PHY = 0xfe,
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};
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struct dw_hdmi_mpll_config {
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unsigned long mpixelclock;
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struct {
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u16 cpce;
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u16 gmp;
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} res[DW_HDMI_RES_MAX];
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};
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struct dw_hdmi_curr_ctrl {
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unsigned long mpixelclock;
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u16 curr[DW_HDMI_RES_MAX];
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};
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struct dw_hdmi_phy_config {
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unsigned long mpixelclock;
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u16 sym_ctr; /*clock symbol and transmitter control*/
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u16 term; /*transmission termination value*/
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u16 vlev_ctr; /* voltage level control */
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};
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struct dw_hdmi_phy_ops {
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int (*init)(struct dw_hdmi *hdmi, void *data,
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struct drm_display_mode *mode);
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void (*disable)(struct dw_hdmi *hdmi, void *data);
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enum drm_connector_status (*read_hpd)(struct dw_hdmi *hdmi, void *data);
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void (*update_hpd)(struct dw_hdmi *hdmi, void *data,
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bool force, bool disabled, bool rxsense);
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void (*setup_hpd)(struct dw_hdmi *hdmi, void *data);
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};
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struct dw_hdmi_plat_data {
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struct regmap *regm;
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enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
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const struct drm_display_mode *mode);
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unsigned long input_bus_format;
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unsigned long input_bus_encoding;
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bool use_drm_infoframe;
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/* Vendor PHY support */
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const struct dw_hdmi_phy_ops *phy_ops;
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const char *phy_name;
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void *phy_data;
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unsigned int phy_force_vendor;
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/* Synopsys PHY support */
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const struct dw_hdmi_mpll_config *mpll_cfg;
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const struct dw_hdmi_curr_ctrl *cur_ctr;
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const struct dw_hdmi_phy_config *phy_config;
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int (*configure_phy)(struct dw_hdmi *hdmi,
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const struct dw_hdmi_plat_data *pdata,
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unsigned long mpixelclock);
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};
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struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
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const struct dw_hdmi_plat_data *plat_data);
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void dw_hdmi_remove(struct dw_hdmi *hdmi);
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void dw_hdmi_unbind(struct dw_hdmi *hdmi);
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struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev,
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struct drm_encoder *encoder,
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const struct dw_hdmi_plat_data *plat_data);
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void dw_hdmi_resume(struct dw_hdmi *hdmi);
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void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense);
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int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn,
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struct device *codec_dev);
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void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate);
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void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt);
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void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, u8 *channel_status);
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void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca);
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void dw_hdmi_audio_enable(struct dw_hdmi *hdmi);
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void dw_hdmi_audio_disable(struct dw_hdmi *hdmi);
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void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi);
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/* PHY configuration */
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void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address);
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void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
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unsigned char addr);
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void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable);
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void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable);
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void dw_hdmi_phy_reset(struct dw_hdmi *hdmi);
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enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
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void *data);
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void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
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bool force, bool disabled, bool rxsense);
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void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data);
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#endif /* __IMX_HDMI_H__ */
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