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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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761b4f694c
Some CPUs don't support icache specific instructions to flush icache lines in broadcast way. We use cpu control registers to flush local icache and use IPI to notify other cores. Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
33 lines
861 B
C
33 lines
861 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_CSKY_CACHE_H
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#define __ASM_CSKY_CACHE_H
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/* bytes per L1 cache line */
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#define L1_CACHE_SHIFT CONFIG_L1_CACHE_SHIFT
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
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#ifndef __ASSEMBLY__
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void dcache_wb_line(unsigned long start);
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void icache_inv_range(unsigned long start, unsigned long end);
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void icache_inv_all(void);
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void local_icache_inv_all(void *priv);
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void dcache_wb_range(unsigned long start, unsigned long end);
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void dcache_wbinv_all(void);
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void cache_wbinv_range(unsigned long start, unsigned long end);
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void cache_wbinv_all(void);
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void dma_wbinv_range(unsigned long start, unsigned long end);
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void dma_inv_range(unsigned long start, unsigned long end);
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void dma_wb_range(unsigned long start, unsigned long end);
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#endif
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#endif /* __ASM_CSKY_CACHE_H */
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