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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c8c4076723
Recent Intel chipsets including Skylake and ApolloLake have a special ITSSPRC register which allows the 8254 PIT to be gated. When gated, the 8254 registers can still be programmed as normal, but there are no IRQ0 timer interrupts. Some products such as the Connex L1430 and exone go Rugged E11 use this register to ship with the PIT gated by default. This causes Linux to fail to boot: Kernel panic - not syncing: IO-APIC + timer doesn't work! Boot with apic=debug and send a report. The panic happens before the framebuffer is initialized, so to the user, it appears as an early boot hang on a black screen. Affected products typically have a BIOS option that can be used to enable the 8254 and make Linux work (Chipset -> South Cluster Configuration -> Miscellaneous Configuration -> 8254 Clock Gating), however it would be best to make Linux support the no-8254 case. Modern sytems allow to discover the TSC and local APIC timer frequencies, so the calibration against the PIT is not required. These systems have always running timers and the local APIC timer works also in deep power states. So the setup of the PIT including the IO-APIC timer interrupt delivery checks are a pointless exercise. Skip the PIT setup and the IO-APIC timer interrupt checks on these systems, which avoids the panic caused by non ticking PITs and also speeds up the boot process. Thanks to Daniel for providing the changelog, initial analysis of the problem and testing against a variety of machines. Reported-by: Daniel Drake <drake@endlessm.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Daniel Drake <drake@endlessm.com> Cc: bp@alien8.de Cc: hpa@zytor.com Cc: linux@endlessm.com Cc: rafael.j.wysocki@intel.com Cc: hdegoede@redhat.com Link: https://lkml.kernel.org/r/20190628072307.24678-1-drake@endlessm.com
133 lines
3.1 KiB
C
133 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 1991,1992,1995 Linus Torvalds
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* Copyright (c) 1994 Alan Modra
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* Copyright (c) 1995 Markus Kuhn
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* Copyright (c) 1996 Ingo Molnar
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* Copyright (c) 1998 Andrea Arcangeli
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* Copyright (c) 2002,2006 Vojtech Pavlik
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* Copyright (c) 2003 Andi Kleen
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*
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*/
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/i8253.h>
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#include <linux/time.h>
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#include <linux/export.h>
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#include <asm/vsyscall.h>
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#include <asm/x86_init.h>
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#include <asm/i8259.h>
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#include <asm/timer.h>
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#include <asm/hpet.h>
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#include <asm/time.h>
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#ifdef CONFIG_X86_64
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__visible volatile unsigned long jiffies __cacheline_aligned_in_smp = INITIAL_JIFFIES;
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#endif
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unsigned long profile_pc(struct pt_regs *regs)
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{
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unsigned long pc = instruction_pointer(regs);
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if (!user_mode(regs) && in_lock_functions(pc)) {
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#ifdef CONFIG_FRAME_POINTER
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return *(unsigned long *)(regs->bp + sizeof(long));
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#else
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unsigned long *sp =
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(unsigned long *)kernel_stack_pointer(regs);
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/*
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* Return address is either directly at stack pointer
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* or above a saved flags. Eflags has bits 22-31 zero,
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* kernel addresses don't.
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*/
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if (sp[0] >> 22)
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return sp[0];
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if (sp[1] >> 22)
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return sp[1];
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#endif
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}
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return pc;
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}
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EXPORT_SYMBOL(profile_pc);
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/*
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* Default timer interrupt handler for PIT/HPET
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*/
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static irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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global_clock_event->event_handler(global_clock_event);
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return IRQ_HANDLED;
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}
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static struct irqaction irq0 = {
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.handler = timer_interrupt,
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.flags = IRQF_NOBALANCING | IRQF_IRQPOLL | IRQF_TIMER,
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.name = "timer"
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};
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static void __init setup_default_timer_irq(void)
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{
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/*
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* Unconditionally register the legacy timer; even without legacy
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* PIC/PIT we need this for the HPET0 in legacy replacement mode.
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*/
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if (setup_irq(0, &irq0))
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pr_info("Failed to register legacy timer interrupt\n");
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}
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/* Default timer init function */
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void __init hpet_time_init(void)
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{
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if (!hpet_enable()) {
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if (!pit_timer_init())
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return;
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}
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setup_default_timer_irq();
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}
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static __init void x86_late_time_init(void)
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{
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x86_init.timers.timer_init();
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/*
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* After PIT/HPET timers init, select and setup
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* the final interrupt mode for delivering IRQs.
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*/
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x86_init.irqs.intr_mode_init();
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tsc_init();
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}
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/*
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* Initialize TSC and delay the periodic timer init to
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* late x86_late_time_init() so ioremap works.
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*/
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void __init time_init(void)
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{
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late_time_init = x86_late_time_init;
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}
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/*
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* Sanity check the vdso related archdata content.
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*/
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void clocksource_arch_init(struct clocksource *cs)
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{
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if (cs->archdata.vclock_mode == VCLOCK_NONE)
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return;
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if (cs->archdata.vclock_mode > VCLOCK_MAX) {
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pr_warn("clocksource %s registered with invalid vclock_mode %d. Disabling vclock.\n",
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cs->name, cs->archdata.vclock_mode);
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cs->archdata.vclock_mode = VCLOCK_NONE;
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}
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if (cs->mask != CLOCKSOURCE_MASK(64)) {
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pr_warn("clocksource %s registered with invalid mask %016llx. Disabling vclock.\n",
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cs->name, cs->mask);
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cs->archdata.vclock_mode = VCLOCK_NONE;
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}
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}
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