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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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7de9cf4740
This patch contains cache and TLB maintenance functions. Signed-off-by: Vincent Chen <vincentc@andestech.com> Signed-off-by: Greentime Hu <greentime@andestech.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
50 lines
1.4 KiB
C
50 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2005-2017 Andes Technology Corporation
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#include <linux/bitops.h>
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#include <linux/cacheinfo.h>
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#include <linux/cpu.h>
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static void ci_leaf_init(struct cacheinfo *this_leaf,
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enum cache_type type, unsigned int level)
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{
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char cache_type = (type & CACHE_TYPE_INST ? ICACHE : DCACHE);
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this_leaf->level = level;
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this_leaf->type = type;
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this_leaf->coherency_line_size = CACHE_LINE_SIZE(cache_type);
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this_leaf->number_of_sets = CACHE_SET(cache_type);;
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this_leaf->ways_of_associativity = CACHE_WAY(cache_type);
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this_leaf->size = this_leaf->number_of_sets *
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this_leaf->coherency_line_size * this_leaf->ways_of_associativity;
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#if defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
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this_leaf->attributes = CACHE_WRITE_THROUGH;
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#else
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this_leaf->attributes = CACHE_WRITE_BACK;
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#endif
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}
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int init_cache_level(unsigned int cpu)
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{
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struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
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/* Only 1 level and I/D cache seperate. */
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this_cpu_ci->num_levels = 1;
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this_cpu_ci->num_leaves = 2;
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return 0;
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}
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int populate_cache_leaves(unsigned int cpu)
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{
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unsigned int level, idx;
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struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
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struct cacheinfo *this_leaf = this_cpu_ci->info_list;
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for (idx = 0, level = 1; level <= this_cpu_ci->num_levels &&
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idx < this_cpu_ci->num_leaves; idx++, level++) {
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ci_leaf_init(this_leaf++, CACHE_TYPE_DATA, level);
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ci_leaf_init(this_leaf++, CACHE_TYPE_INST, level);
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}
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return 0;
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}
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